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ksvd算法（matlab）稀疏表示中训练字典
稀疏表示中用来训练字典的ksvd算法，有demo
- 2020-11-28下载
- 积分：1
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FreeRTOS中文入门手册
FreeRTOS中文入门手册方便初学者入门学习，讲的很好，很值得学习第一章任务管理Designed For Micr。 contr。11exs;概览附录中提供了使用源代码的实用信息小型多任务嵌入式系统简介不同的多任务系统有不同的侧重点。以工作站和桌面电脑为例:·早期的处理器非常昂贵,所以那时的多仟务用于实现在单处理器上支持多用户。这类系统中的调度算法侧重于让每个用户公平共享处理器时间。随着处理器功能越来越强大,价格却更偏宜,所以每个用户都可以独占一个或多个处理器。这类系统的调度算法则设计为计用户可以同时运行多个应用程序,而计算机也不会显得反应迟钝。例如某个用户可能同时运行了一个字处理程序,一个电子表格,一个邮件客户端和一个浏览器,并且期望每个应用程序任何时候都能对输入有足够快的响应时间。桌面电脑的输入处珒可以归类为软实时。为了保证用户的最佳体验,计算机对每个输入的响应应当限定在一个恰当的时间范围——但是如果响应时间超出了限定范闱,并不会让人觉得这合电脑无法使用。比如说,键盘操作必须在键按下后的某个时间内作出明显的提示。但如果按键提示超出了这个时间,会使得这个系统看起来响应人慢,而不致于说这台电脑不能使用。仅仅从单处理器运行多线程这一点来说,实时嵌入式系统中的多任务与桌面电脑的多任务从概念上来讲是相似的。但实时嵌入式系统的侧重点却不同于桌面电脑特别是当嵌入式系统期望提供硬实时行为的时候。硬实时功能必须在给定的时间限制之内完成——如果无法做到即意味着整个系统的绝对失败。汽车的安全气囊触发机制就是一个硬实吋功能的例子。安全气囊在撞击发生后给定时间限制内必须弹出。如果响应时间超出了这个时间限制,会使得驾驶员受到伤害,而这原本是可以避免的大多数嵌入式系统不仅能满足硬实时要求,也能满足软实时要求。Designed For Micr。 contr。11exs;术语说明在屮,每个执行线程都被称为任务。在嵌入式社区屮,对此并没有个公允的术语,但我更喜欢用任务而不是线程,因为从以前的经验米看,线程具有更多的特定含义本章的目的是让读者充分了解:在应用程序中,如何为各仟务分配处理时间。●在任意给定时刻,如何选择任务投入运行。●任务优先级如何影响系统行为。●任务存在哪些状态。此外,还期望能够让读者解:●如何实现一个任务。●如何创建一个或多个任务的实例●如何使用任务参数。如何改变一个已创建任务的优先级●如何删除任务。●如何实现周期性处理。空闲任务何时运行,可以用来干什么本章所介绍的概念是理解如何使用的基础,也是理解基于的应用程序行为方式的基础——因此,本章也是这本书中最为详尽的一章Designed For Micr。 contr。11exs;任务函数任务是由语言数实现的。唯一特别的只是任务的函数原犁,其必须返回而且带有一个指针参数。其数原型参见程序清单。void ATaskFunction( void *pvParameters )程序清单任务函数原型每个任务都是在自己权限氾围内的一个小程序。其具有程序入口,通常会运行在一个死循环中,也不会退出。一个典型的任务结构如程序清单所示。仟务不允许以任何方式从实现函数中返回一一它们绝不能有条语句,也不能执行到函数末尾。如果一个任务不再需要,可以显式地将其删除。这也在程序清单展现个任务函数可以用来创建若干个任务—创建出的任务均是独立的执行实例,拥有属于自己的栈空间,以及属于自己的自动变量栈变量,即任务函数本身定义的变量v。 d ATaskFunction(v。1d* pArameters)/*可以像普通函数一样定义变量。用这个函数创延的每个任务实例都有一个属于自己的 vAria1b1 eExamp1e变量。但如果 varial1e3 xample被定义为 static,这一点则不成立-这种情况下只存在一个变量,所有的任务实例将会共享这个变量。int ivariableExample =0;/*仨务通常实现在一个死循环中。*/for(ii)/*完成任务功能的代码将放在这里。*//*如果任务的具体实现会跳出上面的死循环,则此任务必须在函数运行完之前朋除。传入NUL参数表示删除的是当前任务*vTaskDelete( NULL程序清单典型的任务函数结构Designed For Micr。 contr。11exs;顶层任务状态应用程序可以包含多个任务。如果运行应用程序的微控制器只有一个核那么在任意给定时间,实际上只会有一个仼务被执行。这就意味着一个任务可以有一个或两个状态,即运行状态和非运行状态。我们先考虑这种最简单的模型——但请牢记这其实是过于简单,我们硝后将会看到非运行状态实际上又可划分为若千个子状态。当某个任务处于运行态时,处理器就正在执行它的代码。当一个任务处于非运行态时,该任务进行休眠,它的所有状态都被妥善保存,以便在下一次调试器决定让它进入运行态时可以恢复执行。当任务恢复执行时,其将精确地从离开运行态时正准备执行的那一条指令开始执行。A tasks that areOnly one tasknot currentcan be in theRunning are in theRunning state atNot Running Stateany one timeNot RunningRunning图顶层任务状态及状态转移任务从非运行态转移到运行态被称为切换入或切入或交换入相反,任务从运行态转移到非运行态被称为切换出或切出或交换出的调度器是能让任务切入切出的唯一实体。Designed For Micr。 contr。11exs;创建任务函数创建仟务使用的函数这可能是所有数中最复杂的函数,但不幸的是这也是我们第一个遇到的函数。但我们必须首先掌控任务因为它们是多任务系统中最基本的组件。本书中的所有示例程序都会用到,所以会有人量的例子可以参考。附录:描述川到的数据类型和命名约定。portBASE TYPE xTaskCreate( paTASK CODE pvTaskCodeconst signed port CHAR conist pcNameunsigned portSHORT usstackDepthunsigned portEASE TYPE uxPriorityxTaskHandle *pxCreatedTask程序清单函数原型表参数与返回值参数名描述任务只是永不退出的函数,实现常通常是个死循环。参数只一个指向任务的实现函数的指针效果上仅仅是函数名具有描述性的任务名。这个参数不会被使用。其只是单纯地用于辅助调试。识别一个具有可读性的名字总是比通过句柄来识别容易得多。应用程序可以通讨定义常量来定义任务名的最大长度—一包括结朿符。如果传入的字符串长度超过了这个最大值,字符串将会自动被截断。Designed For Micr。 contr。11exs;当任务创建时,内核会分为每个任务分配属于任务自己的唯一状态。值用于告诉内核为它分配多人的栈空间。这个值指定的是栈空间可以保存多少个字,而不是多少个字节比如说,如果是位宽的栈空间,传入的值为则将会分配字节的栈空间。栈深度乘以栈宽度的绩果万不能超过~个类型变量所能表达的最人值。应川程序通过定义常量来决定空闲任条任用的栈空间大小。在为微控制器架构提供的应用程序中,赋予此常量的值是对所有任务的最小建议值如果你的任务会使用大量栈空间,那么你应当赋予一个更大的值。没有任何简单的方法可以决定一个任务到底需要多大的栈空间。计算出来虽然是可能的,但人多数用户会先简单地赋予一个自认为合理的值,然后利用提供的特性来确证分配的空间既不欠缺也不浪费。第六章包括了一些信息,可以知道如何去查询任务使用了多少栈空问。仟务函数接受一个指向的指钅的值即是传递到任务中的值。这篇文档中的一些范例程序将会示范这个参数可以如何使用指定任务执行的优先级。优先级的取值范围可以从最低优先级到最高优先级是一个由用户定义的常量。优生级号并没有上限除了受限于采用的数据类型和系统的有效内存空间,但最妊使用实际需要的最小数值以避免内在浪费。如果的值超过了,将会导致实际赋给任务的优先级被自动封顶到最大合法值。Designed For Micr。 contr。11exs;用于传出任务的句柄。这个句枢将在调川中对该创建出来的任务进行引用,比如改变任务优先级,或者删除仟务。如果应用程序中不会用到这个任务的包柄,则川以被设为返回值有两个可能的返回值:表明任务创建成功。由于内存堆空间不足,无法分配足够的空间来保存任务结构数据和任务栈,因此无法创建任务。第五章将提供更多有关内存管理方面的信息。例创建任务附录:包含一些关于示例程序生成工具的信息。本例演示了创建并启动两个任务的必要步骤。这两个任务只是周期性地打印输出守符串,采用原始的空循环方式来产生周期延迟。两者在创建时指定了相同的优先级,并且在实现上除输出的字符串外完全一样—程序清单4和程序清单5是这两个仟务对应的实现代码。Designed For Micr。 contr。11ers;
- 2020-12-09下载
- 积分：1
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最大后验概率 MAP 准则matlab源码
最大后验概率 MAP 准则以及matlab源码
- 2020-12-06下载
- 积分：1
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51单片机的步进电机控制，lcd1602显示电机转动方向及转速，用矩阵键盘调整方向及速度，包含c源码及proteus仿真
51单片机的步进电机控制，lcd1602显示电机转动方向及转速，用矩阵键盘调整方向及速度，包含c源码及proteus仿真
- 2020-06-17下载
- 积分：1
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24脉波整流电路的设计与分析
24脉波整流电路的设计与分析
- 2020-12-10下载
- 积分：1
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无刷直流电机全桥驱动电路（原理图+PCB）
无刷直流电机全桥驱动电路，原理图+PCB，PCB带3D视图，方便直观查看PCB。此驱动板可同时独立的驱动两路无刷直流电机。
- 2020-12-06下载
- 积分：1
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mqtt源码及文档
MQTT（Message Queuing Telemetry Transport，消息队列遥测传输）是IBM开发的一个即时通讯协议，有可能成为物联网的重要组成部分。附件包括mqtt源码实现，协议手册
- 2020-12-09下载
- 积分：1
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MATLAB基于肤色模型和模板匹配的人脸定位检测
毕设做的人脸检测，用的是matlab，首先进行了模板匹配的模板制作。在进行模板匹配。
- 2020-11-30下载
- 积分：1
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DISORT-辐射传输
离散坐标辐射传输模型DISORT是Stamnes等在1988年开发出来的，求解平面平行辐射传输的方程，源代码由Fortran编写，在大气科学中应用相当普及。
- 2020-12-12下载
- 积分：1
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altera公司IP核使用手册.PDF
altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用A吉RAContentsChapter 1. About this MegaCore FunctionRelease informat1-1Device Family Support···Introduction.··········FeaturesOpen core plus evaluation1-3Performance···Chapter 2. Getting StartedDesign Flow衡·鲁·,看·,音番2-1Megacore Function walkthrough2-2Create a New quartus II Pi2-2Launch the mega Wizard Plug-in ManagerStep 1: Parameterize2-5Step 2: Set Up SimulationStep 3: Generate..,2-11Simulate the design2-13Compile the design2-13Pa Device2-14Set Up Licensing2-15ppend the license to yourdat file2-15Specify the License File in the Quartus II Software...2-15Example Simulation and Compilation..2-16Example quartus Ii project2-16Example simulation with Test Vectors,,,,,,2-16Chapter 3. SpecificationsyperTransport Technology Overview1HT SyStems3-2HT Flow ControlHyper Transport MegaCore Function SpecificationPhysical InterfaceSynchronization and alignment ...Protocol interfClocking Options.......HyperTransport Mega Core Function Parameters and HT Link Performance3-10Signals3-14CSR Module...3-31OpenCore plus time-Out BehaviorAppendix A. ParametersIntroduction鲁鲁鲁A-1Parameter listsDevice Family and Read Only registers···········,,,,,,,,,,A-1Base Address Registers番鲁,A-2Clocking OptionsA-3Advanced settingso March 2009 Altera corporationHyperTransport MegaCore Function User GuideAppendix B. Stratix Device Pin AssignmentsIntroductionB-1GuidelinesAppendix C. Example designGeneral descriptionAdditional informationRevision historyInto-lHow to Contact alteraInfo-1Typographic Conventions ..........Info-2Hyper Transport MegaCore Function User Guideo March 2009 Altera CorporationA吉RA1. About this MegaCore FunctionRelease InformationTable 1-1 provides information about this release of the Hyper Transport Mega CoretfunctioTable 1-1. Hyper Transport Mega Core Function Release InformationitenlDescription∨ ersion9.0Release dateMarch 2009Ordering codeIP-HTProduct ID(s)0098Vendor iD(s)6AF7Altera verifies that the current version of the quartus@ll software compiles theprevious version of each MegaCore function. Any exceptions to this verification arereported in the Mega Core lP Library release Notes and Errata. Altera does not verifycompilation with Mega Core function versions older than one releaseDevice Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families:Full support means the Mega Core function meets all functional and timingrequirements for the device family and may be used in production designsa Preliminary support means the Mega Core function meets all functionalrequirements, but may still be undergoing timing analysis for the device family;itmay be used in production designs with cautionTable 1-2 shows the level of support offered by the Hyper Transport MegaCorefunction for each of the altera device familiesTable 1-2. Device Family SupportDevice FamilySupportHard Copy Stratix@FullStratixFulStratix IIFulStratix‖GXPreliminaryStratix GXOther device familiesNo supportC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide1-2Chapter 1: About this MegaCore FunctionIntroductionIntroductionThe Hyper Transport Mega Core function implements high-speed packet transfersbetween physical(PhY) and link-layer devices, and is fully compliant with theHyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allowsdesigners to interface to a wide range of Hyper TransportTm technology(hT)enableddevices quickly and easily, including network processors, coprocessors, videochipsets, and ASICsFeaturesThe Hyper Transport Mega Core function has the following features8-bit fully integrated hT end-chain interfacePacket-based protocolDual unidirectional point-to-point linksUp to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction)200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devicesLow-swing differential signaling with 100-Q2 differential impedanceHardware verified with Hyper fransport interfaces on multiple industry standardprocessor and bridge devicesFully parameterized mega core function allows flexible, easy configurationFully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GXevice famillesApplication-side interface uses the Altera AtlanticTM interface standardManages Hr flow control, optimizing performance and ease of useIndependent buffering for each HT virtual channelAutomatic handling of ht ordering rulesStalling of one virtual channel does not delay other virtual channels(subject toorderingFlexible parameterized buffer sizes, allowing customization depending onsystem requirementsUser interface has independent interfaces for the HT virtual channels, allowingindependent user logic designCyclic redundancy code(crc) generation and checking to preserve data integrityIntegrated detection and response to common HT error conditions■ CRC errorsEnd-chain errorsFully integrated HT configuration space includes all required configuration spaceregisters and HT capabilities list registersHyper Transport MegaCore Function User Guideo March 2009 Altera CorporationChapter 1: About this MegaCore FunctionPerformance32-bit and 64-bit support across all base address registers bars)automatically handles all csr space accessesVerilog HDL and VHdL simulation supportOpen Core Plus EvaluationWith the Altera free Open Core Plus evaluation feature, you can perform the followingSimulate the behavior of a mcgafunction(Altera MegaCore function or AMPPmegafunction) within your systema Verify the functionality of your design, as well as quickly and easily evaluate itssize and speedGenerate time-limited device programming files for designs that includeMegaCore functionsProgram a device and verify your design in hardwareYou only need to purchase a license for the Mega Core function when you arecompletely satisfied with its functionality and performance and want to take yourdesign to productiono For more information about Open Core Plus hardware evaluation using theHyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"onpage 3-40 and AN 320: Open Core Plus Evaluation of megafunctionsPerformanceThe Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 showtypical performance and adaptive look-up table (alut) or logic element (LE)usagefor the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, andStratix GX devices respectively, using the Quartus@ II software version 7.1Table 1-3 shows the maximum supported data rates in megabits per second(Mbps)by device family and speed gradeTable 1-3. Maximum Supported Hyper Transport Data Rates (Note 1)Speed GradeDevice Family-36Stratix ll GX devices 1000 Mbps 1000 Mbps 800 MbpsNA(2)N/A(2NA(2)Stratix devices1000 Mbps 1000 Mbps 800 Mbps N/A(2)NA(2)NA(2)Stratix devicesN/A(2N/A(2)00 Mbps 800 Mbps 600 Mbps400 MbpsFlip-Chip packagesStratix devicesNA(2)NA(2)NA(2)600 Mbps400 Mbps400 Mbps(Wire Bond packagesStratix GX devicesN/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2)Notes to table 1-3(1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face(2) Devices ot this speed grade are not ottered in this device familyC March 2009 Altera CorporationHyperTransport Mega Core Function User GuideChapter 1: About this MegaCore FunctionPerformanceTable 1-4 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix II and Stratix II GX devicesTable 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX DevicesParametersMemoryUserRXCombinationalHT Link InterfacePosted Non-Posted Response ClockingALUTSLogicfMAX(MHz) MAx(MHz)Buffers BuffersBuffers Option(12)Registers M4K M512 ( 3)3)Shared3.5005200120500125(4RX/TX/Ref35005200500Ref/x8Shared36005400160500>150RX/TXShared4.0006,00016150RX/TX16Shared4,1006,200500125(4)RX/TX/RefShared4.1006200500125(4Ref/TxShared4.2006400160150RX/TXNotes to table 1-4.Refer to " Clocking Options "on page 3-7 for more information about these options(2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200(3)Figures for -3 speed grade devices only(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided byTable 1-5 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix and Stratix GX devicesTable 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX DevicesUser Interface fmaxParametersUtilizationHT Link fMAX MHz)MHZ)RXRXSpeed GradePosted Non-Posted Response Clocking Option LEsM4KBuffers BuffersBuffers)(2 Blocks.5-66Shared rx/tx/ref1240010073)100734448888Shared Ref/Tx 7, 60014400400100{3)100(3)Shared rxtx7,90016400400>125>100Shared rxtx8.900125>100168Shared Rx/T×Ref9,400124004001003)100316Shared ref/ ix9.500144001003)10073)16Shared rx/x9.700400125Notes to table 1-5:(1)Refer to Clocking Options"on page 3-7 for more information about these options(2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES(3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by fourHyper Transport MegaCore Function User GuideC March 2009 Altera CorporationA吉RA2. Getting StartedDesign FlowTo evaluate the HyperTransport Mega Core function using the Open Core Plus feature,include these steps in your design flowObtain and install the HyperTransport Mega Core functionThe HyperTransport Mega Core function is part of the MegaCore IP Library, which isdistributed with the Quartus ii software and downloadable from the altera websitewww.altera.como For system requirements and installation instructions, refer to Quartus II InstallationLicensing for Windows and Linux Workstations on the Altera website atwww.altera.com/literature/lit-qts.ispFigure 2-1 shows the directory structure after you install the HyperTransportMegaCore function, where is the installation directory. The default installationWindows is C: altera ; on Linux it islopt/alteraFigure 2-1. Directory StructureInstallation directorypContains the Altera MegaCore IP Library and third-party IP coresalteraContains the Altera MegaCore IP LibrarycommonContains shared componentshtContains the Hyper Transport Hyper Transport Megacore function files and documentationdocContains the documentation for the Hyper Transport MegaCore functionlibContains encrypted lower-level design filesexampleContains the design example for the Hyper Transport Mega Core function2. Create a custom variation of the Hyper Transport Mega Core function3. Implement the rest of your design using the design entry method of your choice4. Use the IP functional simulation model to verify the operation of your designo For more information about Ip functional simulation models, refer to the SimulatingAltera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook5. Use the Quartus II software to compile your designC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide2-2Chapter 2: Getting StartedMega Core Function WalkthroughIg You can also generate an Open Core Plus time-limited programming file,which you can use to verify the operation of your design in hardware6. Purchase a license for the hypertransport Mega Core functionAfter you have purchased a license for the Hyper transport mega Core functionfollow these additional steps1. Set up licensing2. Generate a programming file for the Altera device(s)on your board3. Program the Altera device(s)with the completed designMegaCore Function WalkthroughThis walkthrough explains how to create a custom variation using the AlteraHyper Transport IP Toolbench and the Quartus II software, and simulate the functionusing an ip functional simulation model and the modelsim software when you arefinished generating your custom variation of the function, you can incorporate it intoⅴ our overall projectIe IP Toolbench allows you to select only legal combinations of parameters, and warnsou of any invalid configurationsIn this walkthrough you follow these stepsCreate a New Quartus II Projecta Launch the MegaWizard Plug-in Manager■Step1: Parameterizea Step 2: Set Up Simulation■Step3: Generate■ Simulate the designTo generate a wrapper file and Ip functional simulation model using default values,omit the procedure described in"Step 1: Parameterizeon page 2-5Create a New Quartus ll ProjectCreate a new Quartus II project with the New Project Wizard, which specifies theworking directory for the project, assigns the project name, and designates the nameof the top-level design entityTo create a new project, perform the following steps1. On the Windows Start menu, select Programs> Altera> Quartus II tostart the Quartus lI software. Alternatively, you can use the Quartus II Web editionsoftware2. In the Quartus II window, on the File menu, click New Project Wizard. If you didnot turn it off previously, the New Project Wizard Introduction page appears3. On the New Project Wizard Introduction page, click NextHyper Transport MegaCore Function User Guideo March 2009 Altera Corporation
- 2020-12-05下载
- 积分：1
