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FFT和IFFT的MATLAB实现代码
快速傅里叶变换（FFT）和IFFT的MATLAB实现代码,编成了MATLAB函数形式，可以直接进行调用。便于大家学习研究。
- 2020-11-29下载
- 积分：1
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labview modbus.rar
【实例简介】labview编程实现与PLC的modbus通讯，采用labview的DSC模块，创建共享变量，方便快速地建立通讯连接
- 2021-12-04 00:39:19下载
- 积分：1
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认知无线电的matlab仿真
matlab认知无线电仿真代码，AWGN信道，高斯噪声，仿真内容是错误概率-判决门限曲线，错误概率-信噪比曲线。错误概率分为漏检测和错误的警告，因此有四个图。每个图还与理论曲线进行了比较。
- 2020-12-04下载
- 积分：1
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openmv pcb原理图 5积分
openmv开源硬件资料，包括openmv1，openmv2以及openmv3的pcb原理图，sch文件可以用Eagle打开，另外提供pdf文件供快速查看
- 2020-11-28下载
- 积分：1
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HHT 希尔伯特黄变换 Hilbert-Huang transform matlab源码 全
Hilbert-Huang希尔伯特黄变换(HHT)的Matlab实现，亲自验证代码可用，最全版本
- 2021-05-06下载
- 积分：1
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matlab的copula相关程序
matlab的copula相关程序，比较全的资源，用来给大家共享
- 2020-11-27下载
- 积分：1
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STM32/PLC/FX2N/程序/KEIL4/5源码/单片机/仿三菱/断电保持16入16
1、本程序运用C语言，根据三菱PLC_FX2N的通信协议和通信命令，基于主控芯片STM32F103XX（目前在STM32F103RC,STM32F103RD,STM32F103VC,STM32F103VD, STM32F103VE测试通过）上编写运行的程序，可以直接利用三菱编程软件编写梯形图下载运行，无需任何转换。目前至少支持的指令有：（其他指令亲可以自己添加） RST RSTS RSTTC OUT OUTS SET SETS ADD SUB MUL DIV LD LDI LDP LDF AND ANI OR ORI ANDP ANDF ORP ORF ADDP SUBP MULP DIVP MOV MOVP END FEND INC DEC INCP DECP CJ CALL RET INV LD= LD> LD< LD= AND= AND> AND< AND= 编程语言 梯形图 程序容量 8K步 内部寄存器D 8000个 定时器T 256个 记数器C 256个 输入点X 256个 输出点Y 256个 壮态继电器S 600个 辅助继电器M 3071点 M0-M3071 特殊功能： M8000(运行监视触点) M8001(运行监视反触点). M8002(初始化脉冲触点) M8003(初始化脉冲反触点) M8004(错误指示触点) M8011(10毫秒时钟脉冲) M8012(100毫秒时钟脉冲) M8013(1秒时钟脉冲) M8014(1分时钟脉冲) M8020(零位标志) M8021(借位标志) M8022(进位标志) M8029（指令执行结束标志) M8033(内存保持触点) M8034 (禁止输出触点). 更多参考FX2N系列。
- 2019-07-13下载
- 积分：1
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【机器学习】菜菜的sklearn课堂(1-12全课).zip
【机器学习】菜菜的sklearn课堂(1-12全课)，内容包含所有代码，以及讲解的课件
- 2020-12-06下载
- 积分：1
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Tsai标定方法matlab代码
计算机视觉中的标定，所用的方法为Tsai的标定方法，用Matlab进行仿真。
- 2020-12-12下载
- 积分：1
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verilog_IEEE官方标准手册-2005_IEEE_P1364
The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group
- 2020-12-11下载
- 积分：1
