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51单片机+CS5460+12864液晶的单相电能表，含源程序
单相电能表，含源程序、电路图，放心下载。
- 2020-12-04下载
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psasp算例说明
PSASP 算例说明 CEPRI7 CEPRI36 wscc三个经典算例
- 2020-11-29下载
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VINS论文推倒及代码解析
VINS 的功能模块可包括五个部分:数据预处理、初始化、后端非线性优化、闭环检测及闭环优化。代码中主要开启了四个线程,分别是:前端图像跟踪、后端非线性优化(其中初始化和 IMU 预积分在这个线程中)、闭环检测、闭环优化。、总体框架Measurement PreprocessingInitializationCamera(30hz)Feature Detectionnd rackerVisual-lnertialInitializedis- onlySfMAlignmentIMU (100hMU Pre-integrationLocal Visual-Inertial: OldestSliting WindowNewestNonli+、 Keyframe?OptimizationBundle Adjustment II Loop detectionwith RelocalizationStates from Loop ClosureFealure retrievel oop Deleted二二1---11------22===Global Pose Graph4-DoF Pose Graph OptimizationKeyframe DatabaseOptimization图1VINS框架ⅵINS的玏能模块可包括五个部分:数据预处理、初始化、后端非线性优化、闭环检测及闭环优化。代码中主要开启了四个线稈,分别是:前端图像跟踪、后端非线性伉化(其中初始化和IMU预积分在这个线程中)、闭环检测、闭环优化各个功能模块的作用上要有:1.I图像和MU预处理●图像:提取图像 Harris角点,利用金字塔光流跟踪相邻帧,通过 RANSAC去除异常点,最后将跟踪到的特征点push到图像队列中,并通知后端进行处理●IU:将IMU数据进行积分,得到当前时刻的位置、速度和旋转(PVQ),同时计算在后端优化中将用到的相邻帧的预积分增量,及预积分误差的 Jacobian矩阵和协方差项。1.2初始化首先,利用SFM进行纯视觉佔计滑窗內所有帧的位姿及3D点逆深度,最后与IMU预积分进行对齐求解初始化参数1.3后端滑窗优化将视觉约束、IMU约束和闭环约束放在·个大的目标函数中进行非线性优化,求解滑窗内所有帧的PVQ、bias等。L M States in the sliding windowIMU:k States from loop clos1Camera:冷 MU measurements>visual measurements★ Catur图2滑窗优化示意图14闭环检测和优化利用D)BoW进行闭环检测,当检测成功后进行重定位,最后对整个相机轨迹进行闭环优化。U预积分VisionIMUVision图3MU预积分示意图21当前时刻pVQ的连续形式将第k唢和第kl帧之间的所有IMU进行积分,可得第kHI帧的位置、速度和旋转(PVQ),作为视觉估计的初始值,这里的旋转采用的四元数。v△t+k+1∈[k,k+1]rW(at-ba ) -owletbk JtE[k, k+1]n(,-bdt∈[k,k+1]其中,a2和O为ⅠMU测量的加速度和角速度,是在Body自身坐标系, world坐标系是IMU所在的惯导系,上式的旋转公式推导可参考附录10.1。22当前时刻PVQ的中值法离散形式公式(1)给出的是连续吋刻的相机当前PVR的达代公式,为了跟代码致,下面给出基于中值法的公式,这与 Estimator:; processIMg(O函数中的Ps]、Rs]和Vs是一致的,IMU积分出来的第j时刻的物理量可以作为第j帧图像的初始值。tr t+a26t(2)ka,St其中q(a1-ba)-g"+q:+1(a+1-ba)(a;+o;+1)2.3两帧之间PVQ增量的连续形式通过观察公式(1)可知,IvU的预积分需要依赖与第k帧的ν和R,当我们在后端进行非线性优化时,需要迭代更新第κ唢的ν和R,这将导致我们需要根据每次迭代后值重新进行积分,这将非常耗吋。因此,我们考虑将优化变量从第k帧到第κ+1帧的IU预积分项中分离开来,通过对公式(1)左右两侧各乘Rb,可化简为:R(+p2k-=2△)+ak+1b其中DtElk, k+1t∈[k,k+1R k(at-bar)ldt)Wendtt∈[kk+1这样我们就得到了连续时刻的MU预积分公式,可以发现,上式得到的MU预积分的值只与不同时刻的a2和o相关。这里我们需要重新讨论下公式(5)预积分公式,以ab,为例,我们发现它是与MU的bias相关的,而bias也是我们需要优化的变量,这将导致的问题是,当每次迭代时,我们得到一个新的bias,又得根据公式(巧5)重新对第k帧和第k+1帧之间的IMU预积分,非常耗时。这里假设预积分的变化量与bias是线性关系,可以写成:ab,+/6n6ba+/16b+8 8ba +p(6)k+1sb24两帧之间PVQ增量的欧拉法离散形式面给出离散时刻的IMU预积分公式,首先按照论文中采用的欧拉法,给出第i个MU时刻与第i1个IMU时刻的变量关系为b+1k+的6t+元R(P)(1+R(P")(a2-bbn)δt25两帧之间PⅤQ增量的中值法离散形式卜面给出代码中采用的基」中值法的IMU预积分公式,这与 Estimator: processIMUO函数中的 Integration Base: push backo上是一致的。注意这里跟公式(2)是不一样的,这里积分出来的是前后两顿之间的IU增量信息,而公式(2)给出的当前帧时刻的物理量信息+1+B k St +=a, &tbb+1Bi + au1其中a,=slqilai-bai)+qiDi t aitl2.6连续形式下PVQ增量的误差、协方差及 JacobianIMU在每个吋刻积分出来的值是有误差的,下面我们对误差进行分析。首先我们直接给出在t时刻误差项的导数为:sa00016a000000-82(066hkR;0006|=00-(a-bh)0-1192k|+|000|mLL000016ba00101n000018b000F+ozk+ Gt其中:F25×15,G215×2,62x1,n12×,上式推导可参考附录102。下面我们讨论它的作用,将其可以简写为:6之k=F62z+Gtnt根据导数定义可知:62b=1m24-6262+8=62+628t=(+F6t)6z+(Gt6t)nt(11)这里我们对公式(1)的IMU误差运动方程再说明,将上式和EKF对比可知,上式恰好给出了如EKF一般对非线性系统线性化的过程,这里的意义是表示下一个时刻的IMU测量误差与上一个时刻的成线性关系,这样我们根据当前时刻的值,可以预测出下一个时刻的均值和协方差,而公式(1)给出的是均值预测,协方差预测公式如下Pb+6=(1+Ft)P(+Fl6t)7+(G,t)Q(G18t)ot(12)上式给出了协方差的选代公式,初始值Pk=0。其中,Q为表示噪声项的对角协方差矩阵000003000另外根据(11)式可获得诀差项的 Jacobian的迭代公式:(I+F26t)(14)其中 Jacobian的初始值为bk=12.7离散形式的PVQ增量误差分析我们首先直接给出PVQ增量误差在离散形式下的矩阵形式,为了与代码一致,我们修改下变量顺序,这和代码中 midPointIntegration(函数是一致的。(但不知为何计算的V中与前四个噪声项相关的差个负号?)1t fo660f106t‖loeBk+1=0f211f20016bδb0[6b102001rnot000kRkotk+1(15006t0n0000δt其中,推导可参考附录10.3:stE(ak-ba)02-4B+1(kk+121k+1b.)6t|6t2(Rr+ rk+18t2Stn=71=Rk+1(a+1-b)6tWr+ wf1=Ik+11+Gb。)δt-Rn+1(ak+121=-2配+1Stl st21(RK+Ruts)4rula1RrotstStR+1(a1R,+114/+11t28离散形式的PVQ增量误差的 Jacobian和协方差将公式(15)简写为:k+1F15×158215×1+V15×13Q则 Jacobian的迭代公式为k+15×15=F/k(16)其中, Jacobian的初始值为/k=l。这里计算出来的k+1只是为了给后面提供对bias的acoblar。协方差的迭代公式为P+15×15=FPFr+vQv(17)其中,初始值P=0。Q为表示噪声项的对角协方差矩阵:00000000aa000Q18×180a00(18)000000三、后端非线性优化31状态向量状态向量共包括滑动窗口内的n+l1个所有相机的状态(包括位置、朝向、速度、加速度计bias和陀螺仪bias)、 Camera到IMU的外参、m+1个3D点的逆深度X=[xr=pw,vb bpc,q3.2目标函数吗+(喻,2)+2(19)其中三个残差项即误差项分别为边缘化的先验信息、IMU测量残差、视觉的重投影残差。三种残差都是用马氏距离表示。根据《十四讲》中高斯牛顿法,若要计算目标函数的最小值,可以理解为,当优化变量有一个增量后,目标函数值最小,以IU残差为例,可写成如下所示:nin lre2bk, X+8Xrk x)+HSⅩDk+1oXk+1k+1其中HB,为B关于 XIK Jacobian,将上式展开并令关于6X的导数为0,可得增量δx的计算公式:H k 8X=k+1TB那么,公式(28)可写成+∑+∑Tk∑1rc上式中,B为MU预积分噪声项的协方差,P为vual观测的噪声协方差。当MU的噪声协方差P越大时,其信息矩阵Pk,将越小,意味着该MU观测越不可信,换句话说,因MU噪声较大,越不可信IMU预积分数据,而更加相信 visual观测。注意,这里的IMU和vsua协方差的绝对值没有意义,因为考虑得是两者的相对性可将上式继续简化为:(Ap+AB +Acox=bp +bB +bc其中,Ap,AB和Ac为 Hessian矩阵,上述方程称之为增量方程。33MU约束1)残差:两帧之间的PVQ和bias的变化量的差△tx+k+1bk qbk+1bR+1 xyz+g"△t)-Bk(20)sbbbb其中各增量关于bias的 Jacobian可从公式(16)的大 Jacobian中的相应位置获得。上面与代码中 Integration base: evaluateD对应,2)优化变量pb, 0W, Svb ,8ba:,bor Opb,, 80W ,Swb,, bakr, Sba3)Jacobian:计算 Jacobian时,残差对应求偏导对象分别为p6e,6vB,6h,ba],6b,6b
- 2020-12-07下载
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Verilog-IEEE Std 1364 -2005 IEEE Standard
Verilog的IEEE标准，比较新的一个吧应该是IEEE Std 1364 TM-2005(Revision of IEEE Std 1364-2001)lEE Standard for VerilogHardware Description LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyAbstract: The Verilog hardware description language(HDL) is defined in this standard. VerilogHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verificationsynthesis, and testing of hardware designs; the communication of hardware design data; and themaintenance, modification, and procurement of hardware. The primary audiences for this standardare the implementors of tools supporting the language and advanced users of the languageKeywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog,Verilog HDL, verilog PllThe Institute of Electrical and Electronics Engineers, Inc3 Park Avenue. New york. NY 10016-5997 USACopyright@ 2006 by the Institute of Electrical and Electronics Engineers, IncAll rights reserved Published 7 April 2006. Printed in the United states of AmericaIEEE is a registered trademark in the U.S. Patent Trademark Office, owned by the Institute of Electrical and ElectronicsEngineers, IncorporatedVerilog is a registered trademark of Cadence Design Systems, IncPrint:|sBN0-738148504SH95395PDFSBN0-7381-48512SS95395No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.IEEE Standards documents are developed within the IEee Societies and the Standards CoordinatingCommittees of the iEEE Standards Association (IEEE-SA)Standards board The ieee develops its standardsthrough a consensus development process, approved by the american National Standards Institute, which bringstogether volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are notnecessarily members of the Institute and serve without compensation. While the ieee administers the processand establishes rules to promote fairness in the consensus development process, the ieee does not independentlyevaluate, test, or verify the accuracy of any of the information contained in its standards.Use of an IEEE Standard is wholly voluntary. The ieee disclaims liability for any personal injury, property orother damage of any nature whatsoever, whether special, indirect, consequential, or compensatory, directly orindirectly resulting from the publication, use of, or reliance upon this, or any other iEEE Standard documentThe ieee does not warrant or represent the accuracy or content of the material contained herein, and expresslydisclaims any express or implied warranTy, including any implied warranty of merchantability or fitness for a specific purpose, or that the use of the material contained herein is free from patent infringement. IEEE Standardsdocuments are supplied "AS IsThe existence of an IEEE Standard does not imply that there are no other ways to produce, test, measurepurchase, market, or provide other goods and services related to the scope of the IEEE Standard. Furthermore, theviewpoint expressed at the time a standard is approved and issued is subject to change brought about throughdevelopments in the state of the art and comments received from users of the standard Every IeeE Standard issubjected to review at least every five years for revision or reaffirmation. When a document is more than fiveyears old and has not been reaffirmed, it is reasonable to conclude Chat ils contents, although still of some valuedo not wholly reflect the present state of the art. Users are cautioned to check to determine that they have thelatest edition of any IEEE StandardIn publishing and making this document available, the IEeE is not suggesting or rendering professional or otherervices for, or on behalf of, any person or entity. Nor is the Ieee undertaking to perform any dutyother person or entity to another. Any person utilizing this, and any other ieee Standards document, should relupon the advice of a competent professional in determining the exercise of reasonable care in any givencircumstancesInterpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relate tospecific applications. When the need for interpretations is brought to the attention of IEEe, the Institute will initiateaction to prepare appropriate responses. Since ifff Standards represent a consensus of concerned interests, it isimportant to ensure that any interpretation has also received the concurrence of a balance of interests. For thisreason, IEEE and the members of its societies and standards coordinating committees are not able to provide aninstant response to interpretation requests except in those cases where the matter has previously received formalconsideration. At lectures, symposia, seminars, or educational courses, an individual presenting information onIEee standards shall make it clear that his or her views should be considered the personal views of that individuarather than the formal position, explanation, or interpretation of the IeeeComments for revision of IEEE Standards are welcome from any interested party, regardless of membership aftil-iation with IEEE. Suggestions for changes in documents should be in the form of a proposed change of texttogether with appropriate supporting comments Comments on standards and requests for interpretations shouldaddressed toIEEE-SA Standards Board445 Hoes lanePiscataway, NJ 08854USANoTE-Attention is called to the possibility that implementation of this standard may require use of subjectmatter covered by patent rights. By publication of this standard, no position is taken with respect to theexistence or validity of any patent rights in connection therewith. The IEf shall not be responsible foridentifying patents for which a license may be required by an ieee standard or for conducting inquiries into thelegal validity or scope of those patents that are brought to its attentionAuthorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute of Electrical and Electronics Engineers, Inc, provided that the appropriate fee is paid to Copyright ClearanceCenter. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service222 Rosewood Drive, Danvers, MA01923 USA; +19787508400. Permission to photocopy portions of any indi-idual standard for educational classroom use can also be obtained through the Copyright Clearance CenterIntroductionThis introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description LanguageThe Verilog hardware description language(HDL) became an IEEE standard in 1995 as IEEE Std 13641995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standardtextual format for a variety of design tools, including verification simulation, timing analysis, test analysisand synthesis. It is because of these rich features that verilog has been accepted to be the language of choiceby an overwhelming number of integrated circuit(IC)designersVerilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels isessentially provided by the semantics of two data types: nets and variables. Continuous assignments, inwhich expressions of both variables and nets can continuously drive values onto nets, provide the basicstructural construct. Procedural assignments, in which the results of calculations involving variable and netvalues can be stored into variables, provide the basic behavioral construct. a design consists of a set of modules, each of which has an input/output(1/O)interface, and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with netsThe Verilog language is extensible via the programming language interface(PLI)and the verilog procedural interface(VPi) routines. The Pli/vPi is a collection of routines that allows foreign functions to accessinformation contained in a Verilog hdl description of the design and facilitates dynamic interaction withsimulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulationand computer-assisted design(CAD)systems, customized debugging TaskS, delay calculators, andannotatorsThe language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of DefensehiLO-2 successfully combined the gate and register transfer levels of abstraction and supported verificationsimulation, timing analysis, fault simulation, and test generationIn 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independentOpen Verilog International(oVi)was formed to manage and promote Verilog HDL. In 1992, the Board ofDirectors of ovi began an effort to establish Verilog hdl as an ieeE standard. In 1993, the first IEeEworking group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard asIEEE Std 1364-1995After the standardization process was complete, the IEEe P1364 Working Group started looking for feedback from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. Thisled to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identifyoutstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-ing on standardizing System Verilog in 2001, additional issues were identified that could possibly have led toincompatibilities between Verilog 1364 and System Verilog. The IEEE P1364 Working group was established as a subcomittee of the System Verilog P1800 Working Group to help ensure consistent resolution ofsuch issues. The result of this collaborative work is this standard ieee Std 1364-2005Copyright C 2006 IEEE. All rights reservedNotice to usersErrataErrata,ifanyforthisandallotherstandardscanbeaccessedatthefollowingurL:http:/stan-dards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errataperiodicaInterpretationsCurrentinterpretationscanbeaccessedatthefollowingUrl:http:/standards.ieeeorg/reading/ieee/interp/Index. htmlPatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence orvalidity of any patent rights in connection therewith. The IEee shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are brought to its attentionParticipantsAt the time this standard was completed, the ieee P1364 Working group had the following membershipJohny Srouji, IBM, IEEE SyStem verilog Working Group chairTom Fitzpatrick, Mentor Graphics Corporation, ChairNeil Korpusik, Sun Microsystems, Inc, Co-chairStuart sutherland sutherland hdl inc. editorShalom Bresticker, Intel Corporation, Editor through February 2005The Errata Task Force had the following membershipKaren pynopsys,rKurt baty. WFSDB ConsultinDennis marsa. XilinxStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationMike McNamara, Verisity, LtdDennis Brophy, Mentor Graphics CorporationDon Mills, LCDM EngineeringCliff Cummings, Sunburst Design, IncAnders nordstrom, Cadence Design Systems, IncCharles dawson, Cadence Design Systems, IncKaren Pieper, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorpoBrad Pierce, Synopsys, IncRonald goodstein, first shot Logic simulation andSteven Sharp Cadence Design Systems, IncAlec Stanculescu. Fintronic USA IncDesignStuart Sutherland. Sutherland HDL IncMark Hartog, Synopsys incGordon Vreugdenhil, Mentor Graphics CorporationJames Markevitch, Evergreen Technology GroupJason Woolf, Cadence design Systems, IncCopyright C 2006 IEEE. All rights reservedThe behavioral Task Force had the following membership:Steven Sharp, Cadence Design Systems, InC, ChairKurt Baty, WFSDB ConsultingJay lawrence. Cadence design Systems. IncStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationKathryn McKinley, Cadence Design Systems, IncDennis brophy, Mentor graphics corporationMichael mcnamara. Verisity LtdCliff Cummings, Sunburst Design, IncDon Mills, LCDM EngineeringSteven Dovich, Cadence Design Systems, IncMehdi Mohtashemi, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorporationKaren Pieper, Synopsys, IncRonald Goodstein, First Shot Logic Simulation andBrad Pierce, Synopsys, IncDesignDave Rich, Mentor Graphics CorporationKeith Gover, Mentor Graphics CorporationSteven Sharp, Cadence Design Systems, IncMark Hartoog, Synopsys, IncAlec Stanculescu. Fintronic USAEnnis Hawk, Jeda TechnologiesStuart Sutherland. Sutherland hdl. IncAtsushi kasuya, Jcda TechnologicsGordon Vrcugdcnhil, Mentor Graphics CorporationThe PLI Task Force had the following membershipCharles Dawson, Cadence Design Systems, Inc, ChairGhassan Khoory, Synopsys, Inc Co-chairTapati Basu, Synopsys, IncMichael rohleder. Freescale Semiconductor. IncSteven Dovich, Cadence Design Systems, IncRob Slater, Freescale Semiconductor IncRalph duncan, Mentor Graphics CorporationJohn Stickley, Mentor Graphics CorporationJim garnett, Mentor Graphics CorporationStuart Sutherland. Sutherland HDL. incJoao geada CLK Design AutomationBassam Tabbara. Novas software. IncAndrzej litwiniuk, Synopsys, IncJim Vellenga, Cadence Design Systems, IncFrancoise Martinolle, Cadence Design Systems, IncDoug Warmke, Mentor Graphics CorporationSachchidananda Patel, Synopsys, IncIn addition, the working group wishes to recognize the substantial efforts of past contributorsMichael McNamara, Cadence Design Systems, Inc1364 Working Group past chair(through September 2004)Alec Stanculescu, Fintronic USA, 1304 Working Group past vice-chair(through June 2004)Stefen Boyd, Boyd Technology, ETF past co-chair(through November 2004)The following members of the entity balloting commitlee voted on this standard. Balloters may have votedfor approval, disapproval, or abstentionAccelleraIntel CorporationBluespec, Inc.Mentor Graphics CorporationCadence Dcsign Systcms, IncSun microsystems, IncIntronic u.s.aSunburst design, IncIBMSutherland hdl lncInfineon TechnologiesSynopsys, IncCopyright C 2006 IEEE. All rights reservedWhen the IEEE-SA Standards Board approved this standard on 8 November 2005, it had the followingmembershipSteve M. mills. chairRichard h. hulett vice chairDon wright Past chairJudith gorman. secretaryMark d. bowmanWilliam B HopfT W. olsenDennis B. BrophyLowell G. JohnsonGlenn parsonsJoseph brudeHerman KochRonald c. petersenRichard coxJoseph L. Koepfinger*Gary s. RobinsonBob davisDavid J lawFrank stoneJulian forster kDaleep c mohlaMalcolm v thadenJoanna n. gueninPaul nikolichRichard l. townsendS. HalpJoe d. watseRaymond hapemanHoward L, wolfmanAlso included are the following nonvoting Ieee-Sa Standards board liaisonsSatish K. aval, NRC RepresentativeRichard Deblasio, DOE RepresentativeAlan H. Cookson, NIST RepresentativeMichelle d, trIEEE Standards Project EditoCopyright C 2006 IEEE. All rights reservedContentsOverview1. 2 Conventions used in this standard1.3SIption1 4 Use of color in this standard1.5 Contents of this standard1.6 Deprecated clauses……….….….….…1.7 Header file listings....18 Examples…………………1.9PNormative references63. Lexical conventions83.1 Lexical tokens3.2 White space3. 3 Comments中··…·········:···············中·····“:·:·:·4·····“··········3. 4 Operators3. 5 Numberssteger constants3.5.2 Real constants123.5.3 Conversion123.6 Strings123.6. 1 String variable declaration133.6.2 String manipulation133.6.3 Special cha3.7 Identifiers. keds, and syste143.7.1 Escaped identifiers143.7.2 Keywords153.7.3 System tasks and functions3.7.4 Compiler directives153.8 Attrib163.8.1 Examples3.8.2 SyIata typ··4.1 Val214.2 Nets and variables4.2.1 Net declarations4.2.2 Variable declarations4.3V4.3.1g v244.3.2 Veclor net accessibility44.4 Strengths4.4.1 Charge strength4.4.2 Drive strength.....卓········中····“·········:·····················:········254.5 Implicit declarations4.6 Net types………264.6.1 Wire and tri nets264.6.2 Wired nets4.6.3TCopyright C 2006 IEEE. All rights reserved4.6.4 Trio and tri l nets4.6.5 Unresolved nets4.6.6 Supply nets324.7 Regs324.8 Integers, reals, times, and realtime4.8.1 Operators and real numbers4.8.2 Conversion4.9 Arrays4.9.1Net arrays…·中·····:··344.9.2 reg and variable arrays344.9.3 Memories4.10 Parameters…………………354.10.1 Module parameters…364.10.2 Local parameters(localparam““374.10.3 Specify parameters……384. Name spaces…39Expressions……5.1 Operators41Operators with real operands425.1.2 Operator precedence………5.1.3 Using integer numbers in expressions…….445.1.4 Expression evaluation order……2451. 5 Arithmetic operators5.1.6 Arithmetic expressions with regs and integers5. 1.7 Relational operators485.1.8Equ495.1.9 Logical operators…495.1.10 bitw isators505.1.11 Reduction operators5.112 Shift operators…….535. 1. 13 Conditional operator535.1. 14 Concatenations545.2 Operands………5.2. 1 Vector bit-Select and part-select addressing..565.2.2 Array and memory addressing.......,.……5.2.3ings585.3 Minimum, typical, and maximum delay expressions5.4 Expression bit lengths5.4.1 Rules for expression bit lengths65.4.2 Examole of expression bit-length problerpl635.4.3 Example of self-determined expressions.645.5 Signed expressions5.5.1 Rules for expression types.....5.5.2 Steps for evaluating5.5.3 Steps for evaluating an assignment5.54 Handling X and Z in signed expressions………5.6 Assignments and truncation6. Assignments……………686.1 Continuous assignments686. 1. 1 The net declaration assignment6.1.2 The continuous assignment statement·····中···:·:·4·中·····6.1.371Copyright C 2006 IEEE. All rights reserved
- 2021-05-06下载
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条纹二值化，细化，轮廓提取源码
对条纹处理是很复杂的任务，特别是对噪声图像，现在可以对图像滤波，二值化，细化，在提取条文中心线，方便后续处理，如对条纹宽度估计
- 2020-12-04下载
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MMC模块化多电平变换器全套资料+PSCAD仿真
里面有国内外论文20多篇还有两个PSCAD的仿真，绝对超值，还有一篇博士论文由于太大未上传，请搜索《模块组合多电平变换器_MMC_研究_杨晓峰》
- 2020-12-06下载
- 积分：1
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机械工业常用材料性能数据库
机械化工行业常用材料性能查询软件，包括弹性模量，屈服强度，抗拉强度，导热系数，泊松比，硬度，许用应力等等
- 2020-12-02下载
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nsga-ii算法
描述nsga-ii算法的文档，对nsga-ii感兴趣的有帮助
- 2020-12-08下载
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Matlab实现灰度图像转换成RGB图像
用Matlab实现的灰度图像转换成RGB图像，效果不错
- 2020-11-29下载
- 积分：1
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基于FPGA的数字通信实现多路数据时分复用和解复用系统系统
本文档介绍了一种基于FPGA的数字通信多路时分复用和解复用系统，使用硬件描述语言很好的实现了系统功能。第2页共63页AbstractThe system is designed for data multiplexed and de-multiplexed. It is based on TDMThe systern includes the transmitter and the receiver. They are implemented mainly by FPGaThere are three inputs in the transmission system: data from A/converter, DIPI and DIP2The three channels are out serially and time-divisional under the FPgas control. The FPGain the transmitter is divided into four modules which are frequency divider, Barker generator,data multiplexer and voltage display. voltage display is used for processing the data convertedy ADC and sending it to the LED. The serial data are serial shifted into the FPGa in thereceiver. Bit-synchronize and frame-synchronize are both picked up, and then de-multiplexThe FPGA in the receiver is divided into three modules which are digital PLL, datade-multiplexer and voltage display. The transmitter will multiplex four ways of 8-bit paralleldata. The first way is adC data, the second and the third way is generated by dip-key. Theother is Barker code used for frame synchronizing. The receiver will maintain the bitsynchronizing, recognize one frame and de-multiplex three ways data. The essay will discussthe design progress, the programming idea and some problems. Works have to be done by thedesigner are: Specify all system components, Make system specification, Draw systemschematics, Write RTL code according the schematics, Synthesis and simulate the rtl codeDesign the PCBS, Validate the functions of the FPGA on-line.Keywords: DPLL; Frame-synchronize; TDM; Verilog HDl; Serial A/D convert;第3页共63页目录引1数字复接系统简介52数字复接方法及方式2.1数字复接的方法…中中·2.2数字复接的方式………3系统原理和各模块设计………………………63.1系统原理及框图…3.2发端系统设计…3.3收端系统设计…···中··中··中····中·,中………93.4FPGA的设计流程“····“:*·············=·······*·*··3.4.1设计输入···“··++··+··*+··+··+++*···++++·*·+·++34.2设计综合……………………123.4.3仿真验证123.4.4设计实现……123.4.5时序分析123.5发端FPGA设计………………………133.5.1分频模块…翻……143.5.2复接模块……………………………………153.5.3显示模块……………………163.5.4编译与仿伤真…………………183.6收端FPGA设计……………………………………………………193.6.1数字锁相模块…………···→····;··中·······中···········→··············203.6.2解复用模块…··++·*···中+“··“++………………………213.6.3显示模块………………………………………………223.6.4编译与仿真………………………………223.7数字锁相环原理及设计……………………………2338串行AD工作原理………………2539并行D/A的工作原理…263.10 Altera flex10K10介绍………………………………………………………………274系统调试…………………………………………………325 Quartus||软件及 Ver log语言简介…………325.10 artus I软件简介……………………………………………………325.2 Verilog语言简介……………………………………………………………34第4页共63页6结论····“4··+·→··*·*··“······+“·+····“······“··+·+“+·…“*·.·+··+“·+·+·*··…………35谢辞36参考文献·a···.········和··::··中.事…37附录…38docn豆丁www.oocin.com第5页共63页引言数字复接、分接技术发展到80年代已经趋于成熟,形成了完善的EI、T系列。它使得多路低速信号可以在髙速信道中传输,同时提髙信道的利用率。PLD/FPGA是电子设计领域中最具活力和发展前途的一项技术,它的影响丝毫不亚于70年代单片机的发明和使用。可以毫不夸张的讲,PID/FPGA能完成任何数字器件的功能,上至高性能CP,下至简单的74电路,都可以用PLD/FPGA来实现。PLD/FPGA如同一张白纸或是一堆积木,工程师可以通过传统的原理图输入法,或是硬件描述语言自由的设计一个数字系统。通过软件仿真,我们可以事先验证设计的正确性。在PCB完成以后,还可以利用PLD/FPGA的在线修改能力,随时修改设计而不必改动硬件电路。使用PLD/FGA来开发数字电路,可以大大缩短设计时间,减少PCB面积,提高系统的可靠性。,PLD/FGA的这些优点使得PLD/FPGA技术在90年代以后得到飞速的发展,同时也大大推动了EDA软件和硬件描述语言的进步。本设计主要利用了FPGA及 Verilog hdl语言来设计数字复、接分接系统。数字复接系统简介在数字通信网中,为了扩大传输容量和提高传输效率常常需要把若干个低速数字信号合并成为一个高速数字信号,然后再通过高速信道传输,这就是所谓的数字复接技术。数字复接是一种已经非常成熟的技术,广泛地应用于无线通信、光通信和微波接力通信。图1-1数字复接系统方框饜图1-1所示,数字复接系统包括数字复接器( digital multiplexer)和数字分接时钟「定时同定时步复分日恢接复器( digital de- multiplexer)两部分。数字复接器是把两个或多个低速的支路数字信号按照时分复用方式合并成为一路高速的合路数字信号的设备;数字分接器是把合路数字信号分解为原来的支路数字信号的设备。数字复接器是由定时、调整和复接单元所组成;数字分接器是由同步、定时、分接和恢复单元所组成。定时单元给设备提供统一的基准时间信号,同步单元给分接器提供与复接器基准时间同步的时间信号,调整单元负责同步输入的各支路信号。恢复单元与调整单元相对,负贵把分接出来的各支路信号复原第6页共63页2数字复接方法及方式2.1数字复接的方法数字复接的方法主要有按位复接、按字复接和按帧复接三种(1)按位复接按位复接的方法是每次只复接每个支路的·位码,复接后,码序列中的第·位表示第一路中的第一位码;第二位表示第二路的第一位码;以此类推,第N位表示第N路的第一位码。这N位码形成第一时隙。同样,第二时隙是有每路的第二位码复接而成。这种复接方法的特点是设备简单、只需小容量存储,易于实现(2)按字复接按字复接就是每次复接支路的一个字或字节。复接后的码顺序是每个封隙为一路n位码。它的特点是利于多路合成和处理,但要求有较大的存储容量,使得电路较为复杂(3)按帧复接这种方法是每次复接一个之路的一帧数码,它的特点是复接时不破坏原来的帧结构,有利于交换,但要求有更大的存储容量。22数字复接的方式按照复接时各低速信号的情况,复接方式可分为同步复接、异步复接与准同步复接。(1)同步复接同步复接被复接的各个支路信号在时间上是完全同步的。在实际应用中,由于各个支路信号到达的时间不一样,造成支路间的码位相位不同,使得信息不能被正确复接。因此需要对支路进行相位调整。在复接时,要插入帧同步码及其它的业务码。(2)异步复接将没有统一标称频率的不同支路数字信号进行复接的方式成为异步复接。在数字通信中广泛采用这种复接方式。(3)准同步复接准同步复接是指参与复接的各个低速信号使用各自的时钟,但各支路的时钟需要在定的容差范围内。准同步复接实际上是在同步复接的基础上增加了码速调整功能3系统原理和各模块设计3.1系统原理及框图首先介绍系统的工作过程。此数字通信系统分为发端和收端两部分。在发端,FPGA对A①D变换数据、DIP1数据和DIP2数据插入帧同步码,形成一帧,对此帧按位时分复用并串行发送出去。同时,A/D输入端的模拟电压值将通过FPGA的处理,显示在七段数码管上。在收端,FPGA首先从串行码中提取位时钟,然后识别帧同步。当识别出帧同步后,FPGA解复用三路并行码,分别将这三路并行码送到后面的D/A变换器、LED1和LED2同时,第一路并行码通过FGA的处理,显示到七段数码管上。传输帧结构如图3-1所示:第7页共63页帧同步第一路第二路|第三路图3-1传输帧结构总系统框图如图3-2所示:七段数码管七段数码管A/DD/A信道DI P1立FPGA收端FPGALED 1DIP2LED2图3-2总系统框图3.2发端系统设计图3-3是发端系统方框图七数码簣豆丁A/D信道DP1愛端FPGADIP2图3-3发端系统方框图如图3-3所示,发端有三路信号:A/D变换信号、拨码开关1和拨码开关2产生的8位信码。AD变换的信码经过FPGA处理显示到七段译码管上,它代表变换前模拟信号的电压值。由于三路信号都是静态信号,因此输入不用进行码速变挨和码速调轄。输出信号的码速率为256Kbps。发端电路在做PCB时需要单层布线,因此将发端系统板倣成三块小板,分为三个图,分别是发端主图、AD变换图和LED显示图。发端主图如34所示,以发端FPGA为核心,其它功能块逐一实现。为了FGA运行的稳定,要在其周围加入6个滤波电容,电容值为0.1uF。拨码开关与排阻共同构成八位信码,分别接到FPGA的8个I/0端口。复位电路是系统正常运行的必要部分,它由按键开关,电解电容和电阻构成。主图板与AD变换板、LED显示板之间用插针和电线连接。这些插针和电线将为A/D变换板和LED显示第8页共63页板提供电源和通信路径。此外,FPGA还需要配置电路。配置电路在开杌时将配置文件载入到FPGA中,FPGA才可以工作。配置电路由上拉电阻和插座组成,其中,五个端口接到FGA五个配置引脚,他们是:DATA0、 sTATuS、 nCONFIG、 CONF DONE与DCLK。3图AA399999温899998旨若起Ed kDYnizisr含已四=图3-4发端主图原理图A/D变换图如图35所示,要说明的是,这里没有采用并行A/D,而是采用了串行A/D,这样可以节省FPGA的管脚。我使用的ADC型号是TC549。TLC549转换输入端模拟量为数字量,为FPGA提供串行数据。这块板的电源由主图板提供,电源端接到主图板的电源端。TLC549需要一片0.1uF的陶瓷电容为芯片的电源端滤波。在做PCB时,这片电容应靠近芯片的VCC与GND。TLC549的模拟输入量有电位器分压和外部输入,通过单刀双掷开关选择。外部输入的模拟量可以是信号源输出,音频输入等。AA「区YcAy图3-5AD变换图第9页共63页LED显示图如图3-6所示,我用五位LED显示模拟电压值。它可以提供0.0001的显示精度。这五位LED由一位独立LED和一个四LED组组成。这五个LED采用扫描方式显示。扫描显示是LED显示的常用方法。通过五个PNP管控制五个LED分时发光,时隙为32ms。在此时隙下,人眼不会察觉到LED分别点亮,而是同时在亮。此法不仅节省七段译码驱动芯片和FPGA的管脚,而且节约电能。小数点的位置固定不变:因此只需将独立LED的小数点设计为常亮。LED数码管采用共阳极,公共端接PP发射极,PNP集电极接电源,PNP的导通由FPGA控制。七段译码芯片采用DM74LS47,它是一片驱动共阳极LED数码管的芯片。同样,在这片芯片的VCC与GND之间加入0.1uF陶瓷滤波电容和essOyNC 5v In图3-6LED显示图3.3收端系统设计收端系统框图如图3-7所示七段数码管D/A信道收端FPGAED1LED2图3-7收端系统框图
- 2020-12-03下载
- 积分：1
