MicroElectronic Circuit Design
微电子电路设计第五版,Richard C. Jaeger, Traveis N. Blalock编著。FIETH EDITIONMICROELECTRONICHM-M- CIRCUIT DESIGNRICHARD C. JAEGERAuburn UniversityTRAVIS N. BLALOCKUniversity of VirginiaMcGrawEducationGrawEducationMICROELECTRONIC CIRCUIT DESIGN. FIFTH EDITIOPublished by McGraw-Hill Education, 2 Penn Plaza, New York, NY 10121 CopyrightC 2016 by McGraw-Hill EducationAll rights reserved. Printed in the United States of America. Previous editions 2011, 2008, and 2004. No part of thispublication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system,without the prior written consent of McGraw-Hill Education, including, but not limited to, in any network or otherelectronic storage or transmission, or broadcast for distance learninSome ancillaries, including electronic and print components, may not be available to customers outside the United StatesThis book is printed on acid-free pape1234567890DOw/DOw1098765ISBN978-0-07-352960-8MHID0-07-352960-5sident Products markets Kurt LVice President, General Manager, Products Markets: Marty Langece President, Content Design Delivery: Kimberly Meriwether DavidManaging director: Thomas TimpGlobal Publisher Raghu srinivasanDirector. Prodrelopment: RoDirector, Digital Content Development: Thomas Scaife, Ph DProduct develoVincent brashMarketing manager: Nick Mc faddenDirector, Content Design Delivery: Linda avenariusProgram meSchillingContent Project Managers: Jane Mohr, Tammy Juran, and Sandra M. SchneeBuyer: Jennifer PickelDesign: Studio Montage, St Louis, MOContent Licensing Specialist: DeAnna DausenerCompositor: MPS LimitedPrinter.R. DonnellAll credits appearing on page or at the end of the book are considered to be an extension of the copyright pageLibrary of Congress Cataloging-in-Publication DataJaeger. Richard cMicroelectronic circuit design/Richard C. Jaeger, Auburn University,Travis N. Blalock, University of Virginia. --Fifth editionpages cmIncludes bibliographical references and indexISBN978-0-07-352960-8(alk. paper)-ISBN0-07-338045-8(alk. paper)d 1. Integrated circuits--Design and construction. 2. Semiconductors--Design and construction. 3. Electronic circuitesign. I. Blalock, Travis N. Il. TitleTK7874.J3332015621.3815-dc232014040020The Internet addresses listed in the text were accurate at the time of publication. The inclusion of a website does not indicatean endorsement by the authors or McGraw-Hill Education, and McGraw-Hill Education does not guarantee the accuracy ofthe information presented at these siteswww.mhhe.comTOTo Joan, my loving wife and life long partnerRichard C. JaegerIn memory of my father, Professor Theron vaughnBlalock, an inspiration to me and to the countlessstudents whom he mentored both in electronicdesign and in life.Travis n blalockBRIEF CONTENTSPreface xxChapter-by-Chapter Summary XXV12 Operational Amplifier Applications 685PART ONE13 Small-Signal Modeling and LinearSOLID-STATE ELECTRONICS AND DEVICESAmplification 77014 Single-Transistor Amplifiers 8411 Introduction to Electronics 32 Solid-State Electronics 4115 Differential Amplifiers and Operational Amplifier3 Solid-state Diodes and Diode circuits 72Design 9524 Field-Effect Transistors 14416 Analog Integrated Circuit Design Techniques 10315 Bipolar Junction Transistors 21517 Amplifier Frequency Response 111318 Transistor Feedback Amplifiers andPART TWOOscillators 1217DIGITAL ELECTRONICSAPPENDICES6 Introduction to Digital Electronics 2837 Complementary MOS (CMOS) Logic Design 359A Standard Discrete Component Values 12918 MOS Memory Circuits 414B Solid-State Device Models and sPIce simulationParameters 12949 Bipolar Logic Circuits 455C TWo-Port Review 1299PART THREIndex 1303ANALOG ELECTRONICS10 Analog Systems and Ideal OperationalAmplifiers 51711 Nonideal Operational Amplifiers and FeedbackAmplifier Stability 587CONTENTSPreface xxCHAPTER 2Chapter-by-Chapter Summary XXVSOLID-STATE ELECTRONICS 41PART ONE2.1 Solid-State Electronic materials 432.2 Covalent bond model 44SOLID-STATE ELECTRONICS2.3 Drift Currents and mobility inAND DEVICES 1Semiconductors 472.3.1 Drift Currents 47CHAPTER 12.3.2 Mobility 48INTRODUCTION TO ELECTRONICS 32.3.3 Velocity Saturation 482.4 Resistivity of Intrinsic Silicon 491.1 A Brief History of Electronics: From2.5 Impurities in Semiconductors 50Vacuum Tubes to Giga-Scale Integration 52.5.1 Donor Impurities in silicon 511.2 Classification of Electronic Signals 82.5.2 Acceptor Impurities in Silicon 511.2.1 Digital signals 92.6 Electron and hole concentrations in1.2.2 Analog Signals 9Doped semiconductors 511.2.3 A/D and D/A Converters--Bridging2.6.1Type Material (ND >NA)52the analog and Digital2.6.2 p-Type Material (N,A>ND)53Domains 102.7 Mobility and Resistivity in Doped1.3 Notational conventions 12Semiconductors 541.4 Problem-Solving Approach 132.8 Diffusion currents 581.5 Important Concepts from Circuit2. 9 Total Current 59Theory 152.10 Energy Band Model 601.5.1 Voltage and current Division 152.10.1 Electron-Hole pair generation in1.5.2 Thevenin and norton circuitan intrinsic semiconductor 60Representations 162.10.2 Energy Band Model for a Doped1.6 Frequency Spectrum of ElectronicSemiconductor 61Signals 212.10.3 Compensated semiconductors 611.7 Amplifiers 222.11 Overview of Integrated circuit1.7.1 Ideal operational amplifiers 23Fabrication 631.7.2 Amplifier Frequency Response 25Summary 661.8 Element Variations in Circuit Design 26Key Terms 671.8.1 Mathematical modeling ofReference 68Tolerances 26Additional Reading 681.8.2 Worst-Case Analysis 27Problems 688.3 Monte Carlo analysis 291.8.4 Temperature Coefficients 32CHAPTER 31.9 Numeric Precision 34SOLID-STATE DIODES AND DIODE CIRCUITS 72Summary 34Key Terms 353.1 The pn Junction Diode 73References 363.1.1 pn Junction Electrostatics 73Additional Reading 363.1.2 nternal diode currents 77Problems 363.2 The i-v Characteristics of the diode 78VIllContents3.3 The Diode Equation: A Mathematica3.15 Full-Wave Bridge Rectification 123Model for the diode 803.16 Rectifier Comparison and Design3.4 Diode Characteristics under reverse, ZeroTradeoffs 124and forward bias 833.17 Dynamic Switching Behavior of the Diode 1283.4.1 Reverse bias 833.18 Photo diodes, solar cells, and3. 4.2 Zero bias 83Light-Emitting Diodes 1293.4.3 Forward Bias 843.18.1 Photo diodes and3.5 Diode Temperature Coefficient 86Photodetectors 1293.6 Diodes under reverse bias 863.18.2 Power Generation from Solar Cells 1303.6.1 Saturation Current in real3.18. 3 Light-Emitting Diodes(LEDs)13Diodes 87Summary 1323.6.2 Reverse Breakdown 89Key Terms 1333.6.3 Diode model for the breakdownReference 134Region 90Additional Reading 1343.7 pn Junction Capacitance 90Problems 1343.7.1 Reverse bias 903.7.2 Forward Bias 91CHAPTER 43.8 Schottky Barrier Diode 933.9 Diode SPICE Model and layout 93FIELD-EFFECT TRANSISTORS 1443.9.1 Diode Layout 944.1 Characteristics of the MOS Capacitor 1453.10 Diode Circuit Analysis 954.1.1 Accumulation Region 1463.10.1 Load-Line Analysis 964.1.2 Depletion Region 1473.10.2 Analysis Using the Mathematical4.1.3 Inversion Region 147Model for the diode 974.2 The nmos transistor 1473.10.3 The Ideal diode model 1014.2.1 Qualitative i-v Behavior of the3.10.4 Constant Voltage Drop Model 103NMOS Transistor 1483.10.5 Model Comparison and4.2.2 Triode Region Characteristics ofDiscussion 104the nmos transistor 1493.11 Multiple-Diode Circuits 1054.2.3 On Resistance 1523.12 Analysis of Diodes Operating in the4.2.4 Transconductance 153Breakdown Region 1084.2.5 Saturation of the i-v3.12.1 Load-Line Analysis 108Characteristics 1543.12.2 Analysis with the Piecewise4.2.6 Mathematical model in theLinear model 108Saturation (Pinch-off)3.12.3 Voltage regulation 109Region 1553.12.4 Analysis Including Zener4.2.7 Transconductance in saturation 156Resistance 1104.2.8 Channel-Length Modulation 1563.12.5 Line and Load Regulation 1114.2.9 Transfer characteristics and3.13 Half-Wave Rectifier Circuits 112Depletion-Mode MosFETs 1573.13.1 Half-Wave Rectifier with resistor4.2.10 Body Effect or SubstrateLoad 112Sensitivity 1593.13.2 Rectifier Filter Capacitor 1134.3 PMOS Transistors 1603.13.3 Half-Wave Rectifier with rc load 1144.4 MOSFET Circuit Symbols 1623. 13.4 Ripple Voltage and Conduction4.5 Capacitances in MOS Transistors 165Interval 1154.5.1 NMOs Transistor Capacitances in3.13.5 Diode Current 117the Triode region 1653.13.6 Surge Current 1194.5.2 Capacitances in the Saturation3.13.7 Peak-Inverse-Voltage(PlV)Rating 119Region 1663.13.8 Diode Power Dissipation 1194.5.3 Capacitances in Cutoff 1663.13.9 Half-Wave Rectifier with Negative4.6 MOSFET Modeling in SPICE 167Output Voltage 1204.7 MOS Transistor Scaling 1683.14 Full-Wave Rectifier Circuits 1224.7.1 Drain Current 1693. 14.1 Full-Wave Rectifier with Negative4.7.2 Gate Capacitance 169Output Voltage 1234.7.3 Circuit and power densities 169ContentsIX4.7.4 Power-Delay Product 1705.3 The pnp Transistor 2234.7.5 Cutoff Frequency 1705.4 Equivalent Circuit Representations for the4.7.6 High Field Limitations 171Transport Models 2254.7.7 The unified mos transistor model5.5 The i-v Characteristics of the bipolarIncluding High Field Limitations 172Transistor 2264.7.8 Subthreshold conduction 1735.5.1 Output Characteristics 2264.8 MOs Transistor Fabrication and layout5.5.2 Transfer characteristics 227Design Rules 1745.6 The Operating Regions of the Bipolar4.8.1 Minimum Feature size andTransistor 227Alignment Tolerance 1745.7 Transport Model Simplifications 2284.8.2 Mos Transistor Layout 1745.7.1 Simplified Model for the Cutoff4.9 Biasing the NMOS Field-EffectRegion 229Transistor 1785.7.2 Model Simplifications for the4.9.1 Why Do We Need Bias? 178Forward-Active Region 2314.9.2 Four-Resistor Biasing 1805.7.3 Diodes in Bipolar Integrated4.9.3 Constant Gate-Source VoltageCircuits 237Bias 1845.7.4 Simplified Model for the4.9.4 Graphical analysis for theReverse-Active Region 238Q-Point 1845.7.5 Modeling Operation in the4.9.5 Analysis Including Body Effect 184Saturation Region 2404.9.6 Analysis Using the Unified5.8 Nonideal Behavior of the bipolarModel 187Transistor 2434.10 Biasing the PMos Field-Effect Transistor 1885.8.1 Junction Breakdown Voltages 2444.11 The junction Field-Effect Transistor5.8.2 Minority-Carrier Transport in theUFET190Base Region 2444.11.1 The JFET With Bias Applied 195.8.3 Base Transit time 2454.11.2 JFET Channel with Drain-Source5.8.4 Diffusion Capacitance 247Bias 1935.8.5 Frequency Dependence of the4.11.3 n-Channel jfet i-v Characteristics 193Common-Emitter current gain 2484.11.4 The p-Channel JFET 1955.8.6 The Early Effect and Early4.11.5 Circuit Symbols and JFET ModelVoltage 248Summary 1955.8.7 Modeling the Early Effect 2494.11.6 JFET Capacitances 1965.8.8 Origin of the Early Effect 2494.12 JFET Modeling in Spice 1965.9 Transconductance 2504.13 Biasing the JFET and Depletion-Mode5.10 Bipolar Technology and sPiCe Model 251MOSFET 1975.10.1 Qualitative Description 251Summary 2005.10.2 SPICE Model Equations 252Key Terms 2025.10.3 High-Performance BipolarReferences 202Transistors 253Problems 2035.11 Practical bias circuits for the bjt 2545.11.1 Four-Resistor bias network 256CHAPTER 55.11.2 Design Objectives for theBIPOLAR JUNCTION TRANSISTORS 215Four-Resistor bias network 2585.11.3 terative Analysis of the5.1 Physical Structure of the BipolarFour-Resistor bias circuit 262Transistor 2165.12 Tolerances in bias circuits 2625.2 The Transport Model for the npn5. 12.1 Worst-Case Analysis 263Transistor 2175. 12.2 Monte Carlo Analysis 2655.2.1 Forward Characteristics 218Summary 2685.2.2 Reverse Characteristics 220Key Terms 2705.2.3 The Complete Transport ModelReferences 270Equations for Arbitrary BiasProblems 271Conditions 221
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西门子S7-1200 SCL编程指令手册.pdf
西门子1200PLC SCL编程指令手册，详细介绍西直门1200和1500PLC的SCL编程指令R_TRG检测信号上升沿(S7-1200,S7-1500)RTR|G:检测信号上升沿唱圆说明使用检测信号上升沿”指爷,可以检测输入CLK的从“0"到“1”的状态变化。该指合捋输入CLK的当前值与保存在指定实例中的上次查询(边沿存储位)的状态进行比较。如果该指合检测到输入CLK的状态从“03变成了“1”,就会在输出Q中生成一个信号上升沿,输出的值将为TRUE或“1”一个周期。在其它任何情况下,该指合输出的信号状态均为“0”。烀该指合插入程序中时,烀自动打开“调用选项" Call options)对话框。在该对话框中,可以指定将边沿存储位存储在自身数据块中(单背景)或者作为局部变量存储在块接口中(多重背景)。语法“检测信号上升沿”指爷的语法如下所示(CLK:=参数下表列出了“检测信号上升沿”指爷的参数:参数声明数据类型存储区说明CLKInputBOOL、Q、M、D、L|到达信号,查询该信号的边QOutputBOOL1、Q、MAD、L边沿检测的结果示例以下示例说明了该指合的工作原理SCLR TRIG DB"(CLK : -TagIn>Tagout)i输入CLK中变量的上一个状态存储在“ R TRIG DB”变量中。如果在操作数Tagn1和"Tagn2”或在操作数“Tagn3中检测到信号状态从“0变为“1”,则输出“ Tagout_Q的信号状态为“”一个周期。3F_TRG:检测信号下降沿(S7-1200,S7-1500)FTRG检测信号下降沿唱圆说明使用检测信号下降沿”指爷,可以检测输入CLK的从“1”到"0”的状态变化。该指合捋输入CLK的当前值与保存在指定实例中的上次查询(边沿存储位)的状态进行比较。如果该指合检测到输入CLK的状态从“1"变成了“0,就会在输出Q中生成一个信号下降沿,即输出的值烀为TRUE或“1”一个周期。在其它任何情况下,该指合输出的信号状态均为“0”。烀该指合插入程序中时,烀自动打开“调用选项" Call options)对话框。在该对话框中,可以指定将边沿存储位存储在自身数据块中(单背景)或者作为局部变量存储在块接口中(多重背景)。语法“检测信号下降沿”指爷的语法如下所示(CLK:=参数下表列出了“检测信号下降沿指合的参数:参数声明数据类型存储区说明CLKInputBOOLQ,M、D、L到达信号,查询该信号的边沿QOutputBOOLQ、M、D、L|边沿检测的结果示例以下示例说明了该指合的工作原理SCLF TRIG DB(CLK :TagIn2 =>Tagout)输入CLK中变量的上一个状态存储在“FTRG_DB"变量中。如果检测到操作数“Tagn"的信号状态从“1变为“0”,则输出" Tagout"的信号状态为“1"4定时器操作(S7-1200,S7-1500)定时器操作该章节包括以下主题的信息:TP:生成脉冲S7-1200,S7-1500)TON:接通延时(S7-1200S7-1500ToF∴关断延时(S7-1200,S7-1500)●TONR:时间累加器(S7-1200,S7-1500)RESET TIMER:复位定时器(S7-1200,S7-1500)PRESET TIMER:加戟持续时间(S7-1200,S7-1500)°传统(S7-15005TP:生成脉冲(S7-1200,S7-1500)TP:生成脉冲唱圆说明使用“生成脉冲”指合来设置持续时间PT的参数Q。当参数|N的逻辑运算结果(RLO)从0变为“1”(信号上升沿)时,启动该指合。指合启动时,预设的时间PT即开始计时。随后无论输入信号如何改变都会将参数Q设置为时间PT。如果持续时间PT仍在计时,即使检测到新的上升沿,参数Q的信号状态也不会受到影响。可通过ET参数查询当前的时间值。该时间值从T#0s开始,在达到持续时间PT后结束。达到持续时间PT时,且参数|N的信号状态为“0”,则复位参数ET。说明如果程序中未调用定时器(这是因为会忽略定时器),则输出ET会在定时器计时结束后立即返回个常数值。每次调用“生成脉冲指合,都会为其分配一个G定时器用于存储指合数据。对于S7-1200cPUEC定时器是一个 C TIMER或 TP TIME数据类型的结构,可如下声明声明为一个系统数据类型为|C_TMER的数据块(例如,MyEC_TMER●声明为块中“ Static程序段内类型为 TP TIME的局部变量(例如,# MyTP_TIMER)对于S7-1500cPUEC定时器是一个 C TIMER、旧 C LTIMER、 TP TIME或 TP LTIME数据类型的结构,可如下声明声明为一个系统数据类型为 C TIMER或lC_ LTIMER的数据块(例如," MylEC_TIMER”)声明为块中 Static部分的 TP TIME或 TP LTIME类型的局部变量(例如,# MyTP_ TIMER)在程序中插入该指合时,将打开“调用选项” Call options)对话框,可以指定C定时器将存储在自身数据块中(单个背景)或者作为局部变量存储在块接口中(多重背景如果创建了一个单独的数据块则该数据块捋保存到项目树“程序块>系统块"( Program blocks> System blocks)路径中的“程序资源( Program resources)文件夹内。有关本主题的更多信息,请参见“另请参见"。只有在调用该指合且每次都会访问Q或ET输出时,才会更新指爷数据。语法生成脉冲”指合的语法如下所示●系统数据类型为EC_ Timer的数据块(全局DB)SCLTP(IN:=PT:=ET=>●局部变量TP:生成脉冲(S7-1200,87-1500)SCLmoloc1 timer(工NPT:=rQ=>)该指合的语法由以下部分组成参数声明数据类型存储区说明s7-1200S7-1500NBOOLBOOL.M.D.|启动输及脉冲的持续时PTIniTIMETIMEl、Q、M、D、间。LTIMEPT参数的值必须为正数OutputBOOLBOOLQ、M、D、在PT持续时间内保持置位状态的操作数TIMEETOutputMEl、Q、M、DLTIME当前时间值有关有效数据类型的更多信息,请参见“另请参见"。脉冲时序图下图显示了“生成脉冲”指合的脉冲时序图PTPTPTET示例7TP:生成脉冲(S7-1200,S7-1500)以下示例说明了该指爷的工作原理SCLTP DB".TP(IN Tag start,PT :=Tag PresetTime"Tag statusET =>"Tag ElapsedTime")i当“ Tag_ start"操作数的信号状态从“0”变为“1"时,PT参数预设的时间段开始计时,同时"Tag_ Status"操作数置位为“1”。当前时间值存储在 Tag_ ElapsedTime"操作数中8TON:接通延时(S7-1200,S7-1500)TON:接通延时唱圆说明可以使用接通延时”指合捋Q参数的设置延时PT指定的一段时间。当参数N的逻辑运算结果(RLO从“0变为“1”(信号上升沿)时,启动该指合。指合启动时,预设的时间PT即开始计时。超过持续时间PT时,参数Q的信号状态变为“1。只要启动输入仍为“1”,参数Q就保持置位。如果|N参数的信号状态从“1变为"0”,则复位参数Q。当在参数N上检测到一个新的信号上升沿时,将重新启动定时器功能。可通过ET参数查询当前的时间值。该时间值从T#0s开始,在达到持续时间PT后结束。只要参数N的信号状态变为0”,就立即复位ET参数。说明如果程序中未调用定时器(这是因为会忽略定时器),则输出ET会在定时器计时结束后立即返回一个常数值。每次调用“接通延时指合,必须捋其分配给存储指合数据的EC定时器对于S7-1200CPUEC定时器是一个 C TIMER或 TON TIME数据类型的结构,可如下声明●声明为一个系统数据类型为 C TIMER的数据块(例如, MylEC_ TIMER”)●声明为块中“ Static"程序段内类型为 TON TIME的局部变量(例如,# MyTON_TIMER)对于S71500cPUEC定时器是一个|EC_TMER、 EC LTIMER、TON_TME或 TON LTIME数据类型的结构,可如下声明●声明为一个系统数据类型为旧EC_ TIMER或C_ LTIMER的数据块(例如," MylEC_TIMER")声明为块中“ Static"部分的 TON TIME或 TON LTIME类型的局部变量(例如,# My TON_ TIMER)在程序中插入该指合时,捋打开“调用选项( Call options)对话框,可以指定C定时器烀存储在白身数据块中(单个背景)或者作为局部变量存储在块接口中(多重背景)。如果创建了一个单独的数据块,则该数据块捋保存到项目树“程序块>系统块( Program blocks> System blocks)路径中的“程序资源Program resources)文件夹内。有关本主题的更多信息,请参见“另请参见”。只有在调用该指合且每次都会访问Q或ET输出时,才会更新指合数据。语法接通延时指合的语法如下所示●系统数据类型为C_Tmer的数据块(全局DB)SCLTON(N:=PT:=,Q=>,三=>)9TON:接通延时(S7-1200,S7-1500)●局部变量SCLmoloc1 timer(工N:=rPT:=rQ=>ET)该指合的语法由以下部分组成参数声明数据类型存储区说明s7-1200s7-1500NInputBOOLBOOLl、Q、M、D启动输入接通延时的持TIME、Q、M、D、续时间PTInputTIMELTIMEPT参数的值必须为正数定时器PT内时OutputBOOLQ、M、D、间用完时,保持BOOL置位状态的操作数。TIMETIMEQ、M、DETOutputLTIME当前时间值有关有效数据类型的更多信息,请参见“另请参见”。脉冲时序图下图显示了“接通延时指合的脉冲时序图PTET
- 2020-12-03下载
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