MIPI Alliance Specification for D-PHY
MIPI Alliance Specification for D-PHY Version 1.00.00 – 14 May 2009配合“MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2)“ 一起看。http://download.csdn.net/detail/micro_st/4242724Version1.00.0014-May-2009MIPI Alliance Specification for D-PHY2 The material contained herein is not a license, either expressly or impliedly, to any IPR owned or3 controlled by any of the authors or developers of this material or MIPl. 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The use or implementation of the contents of this Document may31 involve or require the use of intellectual property rights ("IPR")including(but not limited to) patents32 patent applications, or copyrights owned by one or more parties, whether or not Members of MIPIMIPI33 does not make any search or investigation for IPR, nor does miPi require or request the disclosure of any34 IPR or claims of IPR as respects the contents of this document or otherwise35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed36 MIPI Alliance. Inc37 c/o IEEE-ISTO38 445 Hoes lane39 Piscataway, NJ0885440 Alin: Board SecretaryCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY42 Contents43 Draft Version 1.00.00-14 May 2009441 Overview1451.2 Purpose.…..,.,.,,.,..472 Terminology…2.1 Definitions162.2 Abbreviations…172.3 Acronyms51 3 D-PHY Introduction523.1 Summary of Phy functionality533.2 Mandatory Functionality················2054 4 Architecture21554.1 Lane modules…564.2 Master and slave2254.3 High Frequency Clock Generation22584.4 Clock lane data lanes and the phy-Protocol interface.224.5 Selectable Lane Options·;····················234.6 Lane Module Types4.6.1 Unidirectional Data Lane…264.6.2 Bi-directional data lanes26634.6.3 Clock lane.274.7 Configurations….7654.7.1 Unidirectional Configurations............664.7.2Bi-Dal Half-Duplex Configurations674.7.3 Mixed Data Lane configurations32Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidential111Ⅴ ersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY695.1Transmission Data Structure,………………………∴335.1.1Data unitsa勹5.1.2 Bit order Serialization and De-Serialization33725.1.3 Encoding and decoding735.1.4 Data Buffering,33745.2 Lane States and Line levels755.3 Operating Modes: Control, High-Speed, and Escape5. 4 High-Speed Data Transmission··········;·5. 41 Burst payload data785.4.2 Start-of-Transmission795.4.3End-of-transmission805.4.4 HS Data Transmission burst.365.5 Bi-directional data Lane turnaround5.6 Escape Mode41835.6.1Remote triggers42845.6.2 Low-Power data Transmission43855.6.3 Ultra-Low Power State865.6.4 Escape Mode State Machine43875.7 High-Speed Clock Transmission885. 8 Clock lane Ultra-Low Power State50959 Global Operation Timing Parameters.……5.10 System Power States56915.11 Initialization56925.12 Calibration5.13 Global Operation Flow Diagram57945.14 Data Rate Dependent Parameters(informative)955. 14.1 Parameters Containing Only UI values965. 14.2 Parameters Containing Time and Ul values59Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY5.14.3 Parameters Containing Only Time Values…………5.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent6 Fault detection611006.1 Contention detection1016.2 Sequence Error Detection.……611026.2.1 SoT Error621036.2.2 SOT Sync Error1046.2.3 EoT Sync Error1056.2. 4 Escape Mode Entry Command error.1066.2.5 LP Transmission Sync error621076.2.6 False Control error1086.3 Protocol Watchdog Timers(informative)62l096.3.1 HS RX Timeout6.3.2HS TX Timeout………………·················+···:··:·················∴62l116.3.3Escape mode timeout62l126.3. 4 Escape Mode Silence Timeout6.3.5 Turnaround errors114 7 Interconnect and Lane Configuration.641157.1 Lane configuration1167.2 Boundary Conditions.....…647.3 Definitions………64l187.4S- parameter Specifications………….651197.5 Characterization Conditions207.6 nterconnect Specifications………1217.6.1 Differential characteristics1227. 6.2 Common-mode characteristics671237.6.3 Intra-Lane Cross-Coupling1247. 6. 4 Mode-Conversion limitsCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY1257.6.5 Inter-Lane Cross-Coupling671267. 6.6 Inter-Lane static skew1277.7 Driver and receiver Characteristics1287.7.1 Differential Characteristics1297. 7.2 Common-Mode characteristics1307.7.3 Mode-Conversion Limits1317.7.4 Inter-Lane Matching132 8 Electrical Characterislics701338.1 Driver characteristics1348.1.1 High-Speed Transmitter1358.1.2 Low-Power Transmitter1368.2 Receiver Characteristic·…············…·······…8301378.2.1 High-Speed Receiver801388.2.2Low- Power receiver.................….….821398.3 Line contention detection1408.4 Input Characteristics8441 9 High-Speed Data-Clock Timing1429.1 High-Speed Clock Timing861439.2 Forward High-Speed Data Transmission Timing871449.2.1 Data-Clock Timing Specifications1459.3 Reverse High-Speed Data Transmission Timing89146 10 Regulatory Requirements91147 Annex A Logical PHY-Protocol Inter face Description(informative)92148A 1 Signal Description149A 2 High-Speed Transmit from the Master Side150A3 High-Speed receive at the slave Sidel00151A 4 High-Speed Transmit from the Slave side152A.5 High-Speed Receive at the Master SideIOICopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY153A6 Low-Power Data Transmission102154A7 Low-Power Data Reception.103155A 8 Turn-around156 Annex B Interconnect Design Guidelines (informative)105157B. 1 Practical distances105158B 2 RF Frequency Bands: Interference.105B3 Transmission Line design160B4 Reference Layer.106161B 5 Printed-Circuit board106162B6 Flex-foils106163B 7 Series resistance106164B 8 Connectors106165 Annex C 8b9b Line Coding for D-PHY(normative)107166C 1 Line Coding Features...·············108167C.1.1Enabled Features for the Protocol108l68C 1. 2 Enabled Features for the Phy108169C2 Coding scheme170C 2.1 8b9b Coding Properties.....108171C 2.2 Data Codes: Basic Code Set……….109C.2.3 Comma Codes: Unique Exception Codes110173C 2.4 Control Codes: Regular Exception Codes…10174C.2.5 Complete Coding Scheme………175C 3 Operation with the D-PhY…11117yload: Data and Control177C.3.2 Details for Hs transmission………112178C.3.3 Details for LP Transmissionl12179C 4 Error Signal180C5 Extended PplCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialⅤ ersion1.00.0014-May-2009MIPI Alliance Specification for D-PHYl81C.6 Complete Code Set.….….l15182Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidentialv111Version1.00.0014-May-2009MIPI Alliance Specification for D-PHYl83Figures184 Figure 1 Universal Lane Module functions21185 Figure2 Two Data Lane PHY Configuration.…………23186 Figure 3 Option Selection Flow Graph4187 Figure 4 Universal Lane Module Architecture25188 Figure 5 Lane Symbol Macros and Symbols Legend189 Figure 6 All Possible Data Lane Types and a basic Unidirectional Clock lane190 Figure 7 Unidirectional Single Data Lane Configuration30191 Figure 8 Unidirectional Multiple Data Lane Configuration without LPDT∴.30192 Figure 9 Two Directions Using Two Independent Unidirectional PHYs without LPDT.........31193 Figure 10 Bidirectional Single Data Lane Configuration31194 Figure 1l Bi-directional Multiple Data Lane Configuration......32195 Figure 12 Mixed Type multiple data Lane Configuration32196 Figure 13 Line level34197 Figure 14 High-Speed Data Transmission in Bursts36198 Figure 15 TX and rX State Machines for High-Speed Data Transmission37Figure16 Turnaround Procedure.……39200 Figure 17 Turnaround State Machine40201 Figure 18 Trigger-Reset Command in Escape Mode202 Figure 19 Two Data Byte Low-Power Data Transmission Example203 Figure 20 Escape Mode State Machine204 Figure2 I Switching the Clock Lane between Clock Transmission and low- Power mode………….47205 Figure 22 High-Speed Clock Transmission State Machine49206 Figure 23 Clock Lane Ultra-Low Power State State Machine········+·+···+·4···207 Figure 24 Data Lane Module State Diagram57208 Figure 25 Clock Lane Module state diagram58209 Figure 26 Point-to-point InterconnectCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidential
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28335芯片中文资料
28335的中文翻译资料，很好，很全面，几乎把英文版的意思都表达到了lEXASINSTRUMENTS寄存器校准多通道缓冲串行端口模块增强型控制器局域网模块和串行通信接口模块串行外设接口模块内部集成电路外部接器件支持器件和开发支持工具命名规则文档支持社区资源电气规范最大绝对额定值建议的运行条件电气特性流耗减少流耗流耗图散热设计考虑在没有针对的信号缓冲的情况下,仿真器连接时序参数符号安排定时参数的通用注释测试负载电路器件时钟表时钟要求和特性电源排序电源管理和监控电路解决方案通用输入输出输出时序输入时序针对输入信号的采样窗口宽度低功耗模式唤陧时序增强型控制外设增强型脉宽调制器时序触发区输入时序高分辨率时序增强型捕捉时序增强型正交编码器脉冲时序转换开始时序外部中断时序电气特性和时序串行外设接口模块主模式时序受控模式时序外部接口时序同步模式异步模式信号与致外部接口读取时序外部接口写入时序版权内容EXASINSTRUMENTS带有一个外部等待状态的外部接口读取准备就绪时序带有一个外部等待状态的外部接口写入准备就绪时序和定时片载模数转挨器加电控制位时序定义顺序采样模式(单通道)同步采样模式(双通道)详细说明多通道缓冲串行端口模块发送和接收时序作为主控或者受控时序闪存定时器件和器件之间的迁移到的修订历史记录到修订历史记录散热和机械数据内容权lEXASINSTRUMENTS图片列表引脚蒲型四方扁平封装(顶视图)焊球(左上象限)(底视图)焊球右上象限)(底视图焊球(左下象限)(底视图焊球(右下象限)(底视图)焊球塑料(左上象限)(底视图)焊球塑料(右上象限)(底视图)焊球塑料(左下象限)(底视图)焊球塑料(右上象限)(底视图)功能方框图内存映射内存映射内存映射外部和中断源外部中断使用块的中断复用时钟和复位域和块方框图使用一个外部振荡器使用一个外部振荡器使用内部振荡器实全装置模块功能方框图定时器定时器屮断信号和输出信号时基计数器同步方案子模块显示关键内部信号互连功能方框图功能方框图模块的方框图带有内部基准的引脚连接带有外部基准的引脚连接模块方框图和接口电路图内存映射内存吹射串行通信接口模块方框图模块方框图(受控模式外设模块接口方框图使用采样窗口的限定外部接口方框图典型的位数据总线连接典型的位数据总线连接的器件命名法示例典型运行电流与频率间的关系(典型运行功率与频率间的关系(版权图片列表EXASINSTRUMENTS在没有针对的信号缓冲的情况下,仿真器连接测试负载电路时钟时序加电复位热复位写入寄存器所产生的效果的示例通用输出时序采样模式通用输入时序进入和退出定时进入和退出时序图使用的唤醒特性或者时序外部中断时序主控模式外部时序(时钟相位)主控模式外部时序(时钟相位)受控模式夕部时序(时钟相位受控模式外部时序(时钟相位)和之间的关系示例读取访问示例写入访问使用同步访问读取的样本使用异步访问读取的样本使用同步访问写入使用异步访问写入外部接口保持波形时序要求加电控制位时序模拟输入阻抗模型顺序采样模式(单通道)时序同步采样模式时序接收时序发送时序作为主控或者受控时的时序:作为主控或者受控时的时序作为主控或者受控时的时序:作为主控或者受控时的时序图片列表权lEXASINSTRUMENTS图表列表碩件特性硬件特性信号说明中闪存扇区的地址中闪存扇区的地址中闪存扇区的地址处理安全代码付置等待状态引导模式选择外设引导加载引脚外设帧寄存器外设帧寄存器外设帧客存器外设帧寄存器器件仿真寄存器外设中断配置和控制奇存器外部中断寄存器,时钟,安全装置,和低功率模式寄存器设置分频选项可能的配置模式低功率模式定时器,,配置和控制寄存器控制和状态寄存器(屮的默认配置)控制和状态寄存器(在中重新映射的配置可由访问)控制和状态奇存器控制和状态寄存器寄存器寄存器汇总收发器寄存器映射寄存器寄存器寄存器寄存器寄存器寄存器复用器外设选择矩阵复用器外设选择矩阵复用器外设选择矩阵配置和控制寄存器映射外设选择指南时电源引脚的流耗为电源引脚的流耗不同外设的典型流耗(在上时)计时和命名规则(器件)版权图表列表EXASINSTRUMENTS计时和命名规则(器件)输入时钟频率时序要求被启用时序要求被禁用开关特性(旁通或者被禁用)电源管哩和监控电路解决方案序要求通用输出开关特性通用输入时序要求模式时序要求模式开关特性模式定时要求模式开关特性模式时序要求模式开关特性时序要求开关特性可编程控制枚障区输入定时要求在时,高分辨率特性增强型捕捉时序要求开关特性增强型正交编码器脉冲时序要求开关特性外部转换开始开关特性外部中断时序要求外部屮断开关特性时序主控模式外部时序(吋钟相位)主控模式外部时序(时钟相位)受控模式外部时序(时钟相位)受空模式外部时序(时钟相位中配置的参数和脉冲持续时间之间的关系时钟配置对于外部存储器接口读取时序要求外部内存接口读取开关特性外部存储器接口写入开关特性外部接口读取开关特性(读取准备就绪,个等待状态)外部接口读取时序要求(读取就绪,个等待状态同步时序要求(读取准各就绪,个等待状态)异步时序要求(读取准各就绪,个等待状态外部接口写入开关特性(写入准备就绪,个等待状态)同步时序要求(写入准各就绪,个等待状态异步时序要求(写入准各就绪,个等待状态)时序要求时序要求电气特性(在推荐的运行条件下)加电延迟不同配置的典型电流消耗(在上)图表列表权lEXASINSTRUMENTS顺序采样模式时序同步采样模式时序时序时要求开关特性作为主控或者受控定时要求作为主控或者受控开关特性主控或者受控时的定时要求作为主控或者受控开关特性作为主控或者受控定时要求作为主控或者受控开关特性作为主控或者受控定时要求作为主控或者受控时的开关侍性对于和温度材料的闪存耐受度闪存对于温度材料的耐受度上的闪存参数:闪存访问时序闪存数据保持持续时间不同频率上所需最小的闪存等待状态散热模型引脚结果散热模型引脚结果散热模型焊球结果散热模型焊球结果版权图表列表TEXASINSTRUMENTS数字信号控制器查询样品特性高性能静态技术增强型控制外设高达周期时间)多达个脉宽调制输出内核,设计高达个支持微边界定位分辨率高性能位的高分辨率脉宽调制器输出单精度浮点单元()(只在高达个事件捕捉输入上提供)多达两个正交编码器接口和双介质方问控制运算高达个位定时器(个以及个)哈佛总线架构高达位定时器快速中断响应和处理个以及个统一存储器编程模型三个位定时器高效代码(使用和汇编语言)串行端口外设通道处理器(用多达个控制器局域网模块和多达模块位或位外部接口高达个模块(可配置为)超过地址范围个模块片载存储器一个内部集成电路总线位模数转换器个通道闪存,转换率通道输入复用器闪存两个采样保持单一同步转换闪存,内部或者外部基准次性可编程多达个具有输入滤波功能可单独编程的多路复用引导通用输入输出引脚支持软件引导模式(通过边界扫描支持和并高级仿真特性标准数学表分析和断点功能时钟和系统控制借助硬件的实时调试支持动态锁相环开发支持包括比率变化片载振荡器编译器汇编语言连接器安全装置定时器模块到引脚可以连接到八个外部内核中断其中的一个数字电机控制和数字电源软件库可支持仝部个外设中断的外设中断扩展块位安全密钥锁保护闪存模块防止固件逆向工程标准标准测试端口和边界扫面架构A版权
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