三相永磁同步电机国标
便于读者对永磁同步电机型式实验项目进行学习，有利于对永磁类电机的技术开发LEPGB/T22669-2008前言本标准参考采用了GB/T1029-2005《三相同步电机试验方法》、GB/T1032—2005《三相异步电动机试验方法》、GB/T13958-2008《无直流励磁绕组同步电动机试验方法》IEC60034-2-1:2007《旋转电机(牵引电机除外)确定损耗和效率的试验方法》和美国标准 IEEE Std112:204《多相感应电动机和发电机试验方法》的相关内容。本标准内容是广泛采用的公认的试验方法适应国际贸易技术交流和经济发展的需要。为满足特殊研究或应用的需要,可按本标准未作规定的附加方法进行试验本标准制定了适用于永磁同步电动机的“B法”测定效率的方法;基准温度采用了IEC6034-21200?的规定;给出了电机性能计算格式等本标准的附录A为规范性附录附录B和附录C为资料性附录。本标准由中国电器工业协会提出本标准由全国旋转电机标准化技术委员会(SAC/TC26)归口。本标准由上海电器科学研究所(集团)有限公可负资起草其他主耍起草单位有:江苏安捷机电技术有限公司、河南特高特电机科技发展有限公司、华北电力大学、广东江门江晟电机有限公司、安徽明腾永磁机电设备有限公司、卧龙电气集团股份有限公司。本标准主要起草人;陈伟华、倪立新、金惟伟、周志民、罗应立、刘华涛、袁福民、鲍周清、朱兴恒温旭、严伟灿、李秀英姚丙雷、张宝强陈亦新本标准为首次发布。EpicGB/T22669-—2008三相永磁同步电动机试验方法范围本标准规定了三相水磁同步电动机的试验方法本标准适用于自起动三相永磁同步电动机,静止变频电源供电的同步电动机试验可参照使用,不适用于有直流励磁绕组的同步电动机。2规范性引用文件下列文件中的条款通过本标准的引用而成为本标准的条款。凡是注日期的引用文件,共随后所有的修改单(不包括勘误的内容)或修订版均不适用于本标准,然而,戴励根据本标准达成协议的各方研究是否可使用这些文件的最新版本。凡是不注日期的引用文件,其最新版本适用于本标准。GB755—2008旋转电机定额和性能(IEC60034-1:2004,IDT)GB/T1029—2005三相同步电机试验方法GB/T10322005三相异步电动机试验方法GB10068—2008轴中心高为56mm及以上电机的机槭振动振动的测量、评定及限值(IEC60034-14:2003,IDT)GB/T10069.1-2006旋转电机噪声测定方法及限值第1部分:旋转电机噪声测定方法ISO1680:1999,MOD)GB/T13958-2008无直流励磁绕组同步电动机试验方法1EC60034-2-1:2007旋转电机(牵引电机除外)确定损耗和效率的标准试验方法3主要符号cosq功率因数电源频率(Hz)I1—定子线电流(A)——空毂线电流(A)Ik—堵转线电流〔A额定电流(A)—直流电机电枢电流(A)K—导体材料在0℃时电阻温度系数的倒数铜K1=235铝K1=225除非另有规定正d——转矩读数修正值(N·m)J——转动惯盘(kg·m2)n—试验时测得的转速(r/min)p一电机的极对数P1-输入功率(W)P2--输出功率(W)Ps--额定(输出)功率(WP铁耗(W)Pt—风摩耗(W)CEPICCB/T22669-2008P—剩余损耗(W)Ps杂散损耗(WPs—空载杂损耗(W)P。—一空载输入功率(W)PK—堵转时的输入功率(WPm—定子绕组在试验温度下P2R损耗(W)Poau空载时在试验温度下定子绕组PR损耗(WPaus—定子绕组在规定温度(0)下IR损耗(WR1——温度为阴1时定子绕组初始端电阻(g)RN-额定负载热试验结束时定子绕组端电阻〔)R:—试验温度下测得(或求得)的定子绕组端电阻()Rs—换算到规定温度()时的定子绕组端电阻(Q)R—-空载试验(锵个电压点)定子绕组端电阻(a)Ta—转矩读数(N·m)T如-—空载(与测力机连接)转矩读数(N·m)T—修正过的转矩(N·m)TK堵转时转矩(N·mT-—在试验电压L,下测得的失步转矩(N·m)TN一一额定电压时的失步转矩(N·m)T—最小转矩(N·mT—在试捡电压U下测得的牵入转矩(N·mTN-一额定电压下的标称牵人转矩N·m)T—异步转矩(N·m)Tx-永磁制动转矩(N·m)U—端电压(v)U。—空载试验端电压(V)Ux堵转试验端电压()Ux—额定电压(v)01—测量初始(玲)电阻R1时的绕组温度℃)a-一额定负载热试验期间测取的定子绕组最高温度℃4-试验时测得的定子绕组最高温度〔℃O.一热试验结束时冷却介质温度(℃日--负载试验时冷却介质温度(℃)标准规定的基准温度(℃0-计算效率时规定的定子绕组温度(℃—空载试验时定子绕组温度(℃)△61--定子绕组温升(K—效率(%)4试验要求4.1试验电游4.1.1电压4.1.1.1电压波形试验电源的谐波电压因数(HVF)应不超过0,02;在进行热试验时应不超过0.015CEpiCCB/T22669-20084.1.1.2电压系统的对称性三相电压系统的负序分量和零序分量均应不超过正序分量的1.0%在进行热试验时,电压系统的负序分量应不超过正序分量的0.5%零序分量的影响应予以排除。4.1.2频率4.1.2.1频率偏差试验期间,电源频率与规定频率之差应在规定频率的士0.3%范围内。1.22频率的稳定性试验期间不允许频率发生快速变化,因为频率快速变化不仅影响被试电机,也会影响到输出测量装置。测量期间频率变化量应小于0.1%42测量仪器4.2.1概述因为大多数仪器的准确度等级通常以满量程的百分数表示。因此,应尽量按实际读数的需要,选择低量程仪表。影响仪器测量结果准确度的因素a)信号源负载;b)引接线校正c)仪器的量程、使用条件和校准。4.2.2电量测量仪器通常,电量测量仪器的准确度应不低于0.5级(满量程,兆欧表除外)。用B法(见10,2,2)测定电机效率时,为保持试验结果的准确性和重复性,要求仪器的准确度等级不低于0.2级(满量程)般来说,电子仪器是多用途的,与无源仪器(非电子式)相比,有非當大的翰入阻抗,无需因仪器自身损耗而修正读数。但高输入阻抗仪器对干扰更为敏感。应依实践经验,采取减少于扰的措施。测盘用仪用互感器的准确度等级应不低于0.2级(满量程)4.2.3转矩测量仪一般试验用转矩测量仪(含测功机和传感器)的准确度等级应不低于0.5级。采用B法(见10.2.2测定效率时,转矩测量仪的准确度等级应不低于0.2级(满量程)4.2.4转速与频率测量仪转速表读数误差在土lr/min以内。频率表的准确度等级应不低于0.1级(满量程)4.2.5电阻测量仪绕组的直流电阻用双臂电桥或单臂电桥,或数字式微欧计测量准确度应不低于0.2级。4.2.6温度测量仪温度测量仪的最大允许误差为士1℃4.3测量要求4.3,1电压测量测量端电压的信号线应接到电机端子,如现场不允许这样连接,应计算由此引起的误差并对读数作校正。取三相电压的算术平均值计算电机性能三相电压的对称性应符合4.1.1.2的要求4.3.2电流测量应同时测量电动机的每相线电流,用三相线电流的算术平均值计算电动机的性能。使用电流互感器时接入二次回路仪器的总阻抗(包括连接导线)应不超过其额定阻抗值对I
- 2021-05-06下载
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altera公司IP核使用手册.PDF
altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用A吉RAContentsChapter 1. About this MegaCore FunctionRelease informat1-1Device Family Support···Introduction.··········FeaturesOpen core plus evaluation1-3Performance···Chapter 2. Getting StartedDesign Flow衡·鲁·,看·,音番2-1Megacore Function walkthrough2-2Create a New quartus II Pi2-2Launch the mega Wizard Plug-in ManagerStep 1: Parameterize2-5Step 2: Set Up SimulationStep 3: Generate..,2-11Simulate the design2-13Compile the design2-13Pa Device2-14Set Up Licensing2-15ppend the license to yourdat file2-15Specify the License File in the Quartus II Software...2-15Example Simulation and Compilation..2-16Example quartus Ii project2-16Example simulation with Test Vectors,,,,,,2-16Chapter 3. SpecificationsyperTransport Technology Overview1HT SyStems3-2HT Flow ControlHyper Transport MegaCore Function SpecificationPhysical InterfaceSynchronization and alignment ...Protocol interfClocking Options.......HyperTransport Mega Core Function Parameters and HT Link Performance3-10Signals3-14CSR Module...3-31OpenCore plus time-Out BehaviorAppendix A. ParametersIntroduction鲁鲁鲁A-1Parameter listsDevice Family and Read Only registers···········,,,,,,,,,,A-1Base Address Registers番鲁,A-2Clocking OptionsA-3Advanced settingso March 2009 Altera corporationHyperTransport MegaCore Function User GuideAppendix B. Stratix Device Pin AssignmentsIntroductionB-1GuidelinesAppendix C. Example designGeneral descriptionAdditional informationRevision historyInto-lHow to Contact alteraInfo-1Typographic Conventions ..........Info-2Hyper Transport MegaCore Function User Guideo March 2009 Altera CorporationA吉RA1. About this MegaCore FunctionRelease InformationTable 1-1 provides information about this release of the Hyper Transport Mega CoretfunctioTable 1-1. Hyper Transport Mega Core Function Release InformationitenlDescription∨ ersion9.0Release dateMarch 2009Ordering codeIP-HTProduct ID(s)0098Vendor iD(s)6AF7Altera verifies that the current version of the quartus@ll software compiles theprevious version of each MegaCore function. Any exceptions to this verification arereported in the Mega Core lP Library release Notes and Errata. Altera does not verifycompilation with Mega Core function versions older than one releaseDevice Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families:Full support means the Mega Core function meets all functional and timingrequirements for the device family and may be used in production designsa Preliminary support means the Mega Core function meets all functionalrequirements, but may still be undergoing timing analysis for the device family;itmay be used in production designs with cautionTable 1-2 shows the level of support offered by the Hyper Transport MegaCorefunction for each of the altera device familiesTable 1-2. Device Family SupportDevice FamilySupportHard Copy Stratix@FullStratixFulStratix IIFulStratix‖GXPreliminaryStratix GXOther device familiesNo supportC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide1-2Chapter 1: About this MegaCore FunctionIntroductionIntroductionThe Hyper Transport Mega Core function implements high-speed packet transfersbetween physical(PhY) and link-layer devices, and is fully compliant with theHyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allowsdesigners to interface to a wide range of Hyper TransportTm technology(hT)enableddevices quickly and easily, including network processors, coprocessors, videochipsets, and ASICsFeaturesThe Hyper Transport Mega Core function has the following features8-bit fully integrated hT end-chain interfacePacket-based protocolDual unidirectional point-to-point linksUp to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction)200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devicesLow-swing differential signaling with 100-Q2 differential impedanceHardware verified with Hyper fransport interfaces on multiple industry standardprocessor and bridge devicesFully parameterized mega core function allows flexible, easy configurationFully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GXevice famillesApplication-side interface uses the Altera AtlanticTM interface standardManages Hr flow control, optimizing performance and ease of useIndependent buffering for each HT virtual channelAutomatic handling of ht ordering rulesStalling of one virtual channel does not delay other virtual channels(subject toorderingFlexible parameterized buffer sizes, allowing customization depending onsystem requirementsUser interface has independent interfaces for the HT virtual channels, allowingindependent user logic designCyclic redundancy code(crc) generation and checking to preserve data integrityIntegrated detection and response to common HT error conditions■ CRC errorsEnd-chain errorsFully integrated HT configuration space includes all required configuration spaceregisters and HT capabilities list registersHyper Transport MegaCore Function User Guideo March 2009 Altera CorporationChapter 1: About this MegaCore FunctionPerformance32-bit and 64-bit support across all base address registers bars)automatically handles all csr space accessesVerilog HDL and VHdL simulation supportOpen Core Plus EvaluationWith the Altera free Open Core Plus evaluation feature, you can perform the followingSimulate the behavior of a mcgafunction(Altera MegaCore function or AMPPmegafunction) within your systema Verify the functionality of your design, as well as quickly and easily evaluate itssize and speedGenerate time-limited device programming files for designs that includeMegaCore functionsProgram a device and verify your design in hardwareYou only need to purchase a license for the Mega Core function when you arecompletely satisfied with its functionality and performance and want to take yourdesign to productiono For more information about Open Core Plus hardware evaluation using theHyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"onpage 3-40 and AN 320: Open Core Plus Evaluation of megafunctionsPerformanceThe Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 showtypical performance and adaptive look-up table (alut) or logic element (LE)usagefor the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, andStratix GX devices respectively, using the Quartus@ II software version 7.1Table 1-3 shows the maximum supported data rates in megabits per second(Mbps)by device family and speed gradeTable 1-3. Maximum Supported Hyper Transport Data Rates (Note 1)Speed GradeDevice Family-36Stratix ll GX devices 1000 Mbps 1000 Mbps 800 MbpsNA(2)N/A(2NA(2)Stratix devices1000 Mbps 1000 Mbps 800 Mbps N/A(2)NA(2)NA(2)Stratix devicesN/A(2N/A(2)00 Mbps 800 Mbps 600 Mbps400 MbpsFlip-Chip packagesStratix devicesNA(2)NA(2)NA(2)600 Mbps400 Mbps400 Mbps(Wire Bond packagesStratix GX devicesN/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2)Notes to table 1-3(1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face(2) Devices ot this speed grade are not ottered in this device familyC March 2009 Altera CorporationHyperTransport Mega Core Function User GuideChapter 1: About this MegaCore FunctionPerformanceTable 1-4 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix II and Stratix II GX devicesTable 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX DevicesParametersMemoryUserRXCombinationalHT Link InterfacePosted Non-Posted Response ClockingALUTSLogicfMAX(MHz) MAx(MHz)Buffers BuffersBuffers Option(12)Registers M4K M512 ( 3)3)Shared3.5005200120500125(4RX/TX/Ref35005200500Ref/x8Shared36005400160500>150RX/TXShared4.0006,00016150RX/TX16Shared4,1006,200500125(4)RX/TX/RefShared4.1006200500125(4Ref/TxShared4.2006400160150RX/TXNotes to table 1-4.Refer to " Clocking Options "on page 3-7 for more information about these options(2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200(3)Figures for -3 speed grade devices only(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided byTable 1-5 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix and Stratix GX devicesTable 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX DevicesUser Interface fmaxParametersUtilizationHT Link fMAX MHz)MHZ)RXRXSpeed GradePosted Non-Posted Response Clocking Option LEsM4KBuffers BuffersBuffers)(2 Blocks.5-66Shared rx/tx/ref1240010073)100734448888Shared Ref/Tx 7, 60014400400100{3)100(3)Shared rxtx7,90016400400>125>100Shared rxtx8.900125>100168Shared Rx/T×Ref9,400124004001003)100316Shared ref/ ix9.500144001003)10073)16Shared rx/x9.700400125Notes to table 1-5:(1)Refer to Clocking Options"on page 3-7 for more information about these options(2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES(3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by fourHyper Transport MegaCore Function User GuideC March 2009 Altera CorporationA吉RA2. Getting StartedDesign FlowTo evaluate the HyperTransport Mega Core function using the Open Core Plus feature,include these steps in your design flowObtain and install the HyperTransport Mega Core functionThe HyperTransport Mega Core function is part of the MegaCore IP Library, which isdistributed with the Quartus ii software and downloadable from the altera websitewww.altera.como For system requirements and installation instructions, refer to Quartus II InstallationLicensing for Windows and Linux Workstations on the Altera website atwww.altera.com/literature/lit-qts.ispFigure 2-1 shows the directory structure after you install the HyperTransportMegaCore function, where is the installation directory. The default installationWindows is C: altera ; on Linux it islopt/alteraFigure 2-1. Directory StructureInstallation directorypContains the Altera MegaCore IP Library and third-party IP coresalteraContains the Altera MegaCore IP LibrarycommonContains shared componentshtContains the Hyper Transport Hyper Transport Megacore function files and documentationdocContains the documentation for the Hyper Transport MegaCore functionlibContains encrypted lower-level design filesexampleContains the design example for the Hyper Transport Mega Core function2. Create a custom variation of the Hyper Transport Mega Core function3. Implement the rest of your design using the design entry method of your choice4. Use the IP functional simulation model to verify the operation of your designo For more information about Ip functional simulation models, refer to the SimulatingAltera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook5. Use the Quartus II software to compile your designC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide2-2Chapter 2: Getting StartedMega Core Function WalkthroughIg You can also generate an Open Core Plus time-limited programming file,which you can use to verify the operation of your design in hardware6. Purchase a license for the hypertransport Mega Core functionAfter you have purchased a license for the Hyper transport mega Core functionfollow these additional steps1. Set up licensing2. Generate a programming file for the Altera device(s)on your board3. Program the Altera device(s)with the completed designMegaCore Function WalkthroughThis walkthrough explains how to create a custom variation using the AlteraHyper Transport IP Toolbench and the Quartus II software, and simulate the functionusing an ip functional simulation model and the modelsim software when you arefinished generating your custom variation of the function, you can incorporate it intoⅴ our overall projectIe IP Toolbench allows you to select only legal combinations of parameters, and warnsou of any invalid configurationsIn this walkthrough you follow these stepsCreate a New Quartus II Projecta Launch the MegaWizard Plug-in Manager■Step1: Parameterizea Step 2: Set Up Simulation■Step3: Generate■ Simulate the designTo generate a wrapper file and Ip functional simulation model using default values,omit the procedure described in"Step 1: Parameterizeon page 2-5Create a New Quartus ll ProjectCreate a new Quartus II project with the New Project Wizard, which specifies theworking directory for the project, assigns the project name, and designates the nameof the top-level design entityTo create a new project, perform the following steps1. On the Windows Start menu, select Programs> Altera> Quartus II tostart the Quartus lI software. Alternatively, you can use the Quartus II Web editionsoftware2. In the Quartus II window, on the File menu, click New Project Wizard. If you didnot turn it off previously, the New Project Wizard Introduction page appears3. On the New Project Wizard Introduction page, click NextHyper Transport MegaCore Function User Guideo March 2009 Altera Corporation
- 2020-12-05下载
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