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基于celp算法的语音编码
该算法是基于matlab软件平台上实现的，实现语音编码
- 2020-12-04下载
- 积分：1
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银行系统项目设计文档(详细文档)
银行系统项目设计文档(详细文档)编写虚拟社区遇到的困难及解决方法 在编码的第一开始，我们就遇到了巨大的难题，分工是很细致了，但是如何来让每个人编写的代码其他人都能用呢？ 这时候我们才发现设计和分工不是最难的，最难的是合作，但是我们并不惧怕困难，先考虑各个人编写的代码其他那几个人用得到，自己编码时要用到别人的那些代码，同时个人编码之前先写好Public 类名以及需要参数和返回参数。这样别人子要知道如何调用函数就行了。在对数据库操作方面我们也屡屡出错，为此我们到图书馆找来数据库SQL方面的书进行学习。后来，我们在RMI远程调用方面也遇到了问题。及使用安全策略文件来设置Java程序权限的问题
- 2021-05-06下载
- 积分：1
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MATLAB图像纹理特征提取代码
用共生矩阵进行纹理特征提取**************************************************************************% 图像检索——纹理特征%基于共生矩阵纹理特征提取，d=1,θ=0°,45°,90°,135°共四个矩阵%所用图像灰度级均为256%参考《基于颜色空间和纹理特征的图像检索》%function : T=Texture(Image) %Image : 输入图像数据%T : 返回八维纹理特征行向量%******************************
- 2020-06-28下载
- 积分：1
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最小二乘拟合matlab程序
最小二乘拟合程序matlab源代码，matlab线性最小二乘逼近的求法求解！！
- 2020-11-30下载
- 积分：1
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TIMIT语音数据库
常用TIMIT语音数据库，在语音信号处理方面非常实用，都是WAV文件，可直接调用
- 2020-12-04下载
- 积分：1
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STM32定时器触发ADC采集，数据发送至上位机.zip
【实例简介】STM32用的F103，定时器用的TIM2，CH2，程序里用的是0.5ms采集一次，在定时器初始化里也可以自己设置
- 2021-12-15 00:32:36下载
- 积分：1
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16×64LED点阵显示屏的设计(附完整proteus仿真图和源程序)
16×64LED点阵显示屏的设计(附完整proteus仿真图和源程序)答辩记录1、例举设计过程中遇到的问题及其解决方法(至少两例)。答:(1)问题说明:解决方法:(2)问题说明:解决方法2、教师现场提的问题记录在此(不少丁2个问题)《单片机原理及应用》课程设计摘要LED电子显示屏是利川发光二极管构成的点阵模块或像素单元组成可变面积的显示屏幕,在信息显示领域得到了广泛的应用,实现显示屏的技术也有很多和。本文介绍了基于单片机80C51为控制器的16×64LED点阵显示屏系统的设计。整机以美国 ATMEL公司生产的40脚单片机AT89C51为核心,介绍了以它为控制系统的LED点阵电子显示屏的动态设计和开发过程。通过该芯片控制一个行驱动器74LS154和八个列驱动器74HC595米驱动显示屏显示。该电子显示屏可以显示各种文字或单色图像,全屏能显示4个汉字,采用16块8×8点阼LED显示模块来组成一个16×64点阼显示模式。显示采用动态显示,使得图形或文字能够实现静止、移入移出等多种显示方式。本文介绍了利用 Proteus7.10软件进行原理图的绘制,利用汉字转换软件将汉字转换为将要发送给单片机的点阵数据,在keil软件当中采用C语言编程,与 proteus进行联调,并通过仿真软件Proteus7.10最终实现自己设想的效果,总体上系统的设计简单、显示清晰、成本较低。关键词:单片机;LED;点阼屏;c语言《单片机原理及应用》课程设计目录摘要设计任务基本要求选做设计方案点阵屏显示模块原理数据传输方案系统硬件电路的设计单片机系统及外围电路点阵显示屏设计点阵显示器的扫描驱动系统软件的设计显示驱动程序系统主程序总结参考文献附录:总设计图附录:总源程序《单片机原理及应用》课程设计设计任务从LED材料的不断更新,灰度控制技术的发展,真彩色图像的展现:到驱动电路的灵活、高效,控制系统技术的提高无不体现了LED行业技术的飞跃发展另外,随着计算机的网路技术的发展,LE显示屏在网路环境下的使用情况越来越多,在多媒体、多和显示设备组成的信息显示系统中,采用智能化网路控制,联网控制多屏技术也在实际屮得到应用。本文讨论了利用单片机为控制信号完成一个点阵显示屏系统的设计。11基本要求设计一款能够显示不同字符的点阵广告牌;2.设计不同的字符切换效果(如內烁,静止,平移等);设计控制按钮,可以在不同的效果间切换;12选做4能够显示图形或自定义字符5通过串行口从电脑上下载更新需显示的字符6其他功能(创新部分)图示例图《单片机原理及应用》课程设计设计方案21点阵屏显示模块原理四个8×8的点阵构成一个16×16的点阵,共由256个LED构成。如果LED的阴极与行相连,而阳极与列相连,那么只要给该LED对应的行以低电平,列以高电平,那么对应的LED就发光。图2-1画岀了可显示一个汉字的16×16的点阵屏模块。这种模块由256个发光LED以16×16的形式构成一个正方形模块,然后引出2列16针的引脚将内部电路接口引出,供驱动电路使用0200100fFC200生400gfEO004000800100TFFE010010001000005000200图2.1LED点阵显示原理图行对应的给LED的阴极,先给第一行以低电平,如果送给16列的代码为0200,则第一行的第7个LED被点亮,再给第二行以低电平,如果送给16列的代码为0100,则第二行的第8个被点亮,接着给第三行以低电平,同时给列以动代码,这样不断地进行行行的扫摧,只要速度够快,由于人的祧觉暂留作用,就不会感觉釗明显的闪烁感。点阵上会看到一个清晰的“字”字《单片机原理及应用》课程设计22数据传输方案显然,采用并行方式时,从控制电路到列驱动器的线路数量大,相应的硬件数目多。当列数很多时,并列传输的方案是不可取的。采用牛行传输的方法,控制电路可以只用根信号线,将列数据位一位传往列驱动器,在硬件方面无疑是卜分经济的。但是,串行传输过程较长,数据按顺序一位一位地输出给列驱动器,只有当一行的各列数据都以传输到位之后,这行的各列才能并行地进行显小。这样,对于一行的显小过程就可以分解成列数据准备(传输)和列数据显示两部分。对于串行传输方式来说,列数据准备时间可能相当长,在行扫描周期确定的情况下留给行显示的时间就人少了,以致影响到LED的亮度。解决串行传输中列数据准备和列数据显示的时间矛盾问题,可以采用重叠处理的方法。即在显示本行各列数据的同时,传送下一列数据。为了达到重叠处理的目的,列数据的显示就需要具有所存功能。经过上述分析,就可以归纳出列驱动器电路应具有的功能。对于列数据准备来说,它应能实现串入并处的移位功能;对于列数据显示来说,应具有并行锁存的功能。这样,本行已准备好的数据打入并行锁存器进行显示时,串并移位寄存器就可以准备下一行的列数据,而不会影响行的显示。图22为显示屏电路实现的结构框图列驱动列驱动列驱动列驱动单片机控制器行驱动6×6LED16×⊥6LED16×16LED6×6LED点阵点阵点阵点阵图点阵显示屏系统框图《单片机原理及应用》课程设计系统硬件电路的设计本系统采用单片机作控制器。整个电路主要由单片机控制及其接口电路、驱动显小电路、电源电路等部分纽成。为了简化显示屏电路,降低成本,本系统在单片机部分不加字库存储器,而在机上编辑汉字和字符显示信息,并将其转换为相应的点阵显示数据。然后通过串口送给单片机存储并进行显示处理使件电路大致上可以分成单片机系统及外围电路、列驱动电路和行驱动电路部分。31单片机系统及外围电路单片机采用MSC-51或其兼容系列芯片,采用24MHZ或更高频率晶振,以获得较高的刷新频率,时期显小更稳定。单片机的串口与列动器相连,用来显小数据。P1口低4位与行驱动器相连,送出行选信号;P1.5~P1.7口则用来发送控制信号MSC51单片机部分管脚说明如下:P0口:P0口为一个8位漏级开路刈向I/0口,每脚可吸收8TTL门电流。当P凵的管脚第次写1时,被定义为高阻输入。P0能够用于外部程序薮据存储器,它可以被定义为数据/地址的第八位P1凵:P1凵是一个内部提供上拉电阻的8位双向I/0凵,P1凵缓冲器能接收输出4L门电流。P1口管脚写入1后,被内部上拉为高,可用作输入,P1口被外部下拉为低电平时,将输出电流,这是由于内部上拉的缘故。在 FLASH编程和校验时,P1口作为第八位地址接收P2凵:P2凵为一个内部上拉电阻的8位双向I0凵,P2凵缓冲器可接收输出4个TL门流,当P2口被写“1”时,其管脚被内部上拉电阻拉高,且作为输入。并因此作为输入时,P2口的管脚被外部拉低,将《单片机原理及应用》课程设计输出电流。这是由于内部上拉的缘故。P2口当用于外部程序存储器或16位地址外部数据存储器进行存取时,P2口输出地址的高八位。在给出地址“I”时,它利用内部上拉优势,当对外部八位地址数据存储器进行读写时,P2凵输出其特殊功能寄存器的内谷。P2凵在 FLASH编程和校验时接收高八位地址信号和控制信号。P3口:P3口管脚是8个带内部上拉电阻的双向I/0口,可接收输出4个TTL门电流。当P3凵写入“1”后,它们被内部上拉为髙电平,并用作输入。作为输入,由亍外部下拉为低电平,P3凵将输出电流(IL)这是由于上拉的缘故RST:复位输入。当振荡器复位器件时,要保持RST脚两个机器周期的高电平时间XTAL1:反向振荡放大器的输入及内部时钟工作电路的输入。XTAL2:来自反向振荡器的输出。CF气x1灯TAP0ADD□P0.2/AD236C2F4/D4F0.5AD5PO, 3JAD6RSTPO.7/A07A3t4C3H山ARo 1nFP2.2A10PSENP2.3A|1ALEF2.4inP2541328P25A1427P27A|5P123P3. 0/RXD F10F1.1/2EP3. ITXDP3 2/NT0F13P1361. 4P34/014P3 6R16PC/FD17B9C54图单片机最小系统原理图
- 2020-12-12下载
- 积分：1
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植物大战僵尸java游戏
植物大战僵尸java游戏植物大战僵尸java游戏植物大战僵尸java游戏
- 2020-12-02下载
- 积分：1
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88E1116R_Datasheet
88E1116R_Datasheet，marvell以太网phy芯片手册，全本88E1116RM A RV E LL. Alaska Gigabit Ethernet TransceiverOVERVIEWFEATURESThe Alaska 88E1116R Gigabit Ethernet Transceiver is10/100/1000BASE-TIEEE 802.3 complianta physical layer device containing a single GigabitSupports reduced pin count GMII(RGMID)interfaceEthernet transceiver. The transceiver implements theFour RGMii timing modesEthernet physical layer portion of the 1000BASE-T,100BASE-TX. and 10base-t standards. t is manufacIntegrated mdi interface termination resistors thateliminate twelve passive componentstured using standard digital CMOS process and con-tains all the active circuitry required to implement theEnergy Detect and Energy Detect+ low powerphysical layer functions to transmit and receive data onmodesstandard Cat 5 unshielded twisted pairThree loopback modes for diagnosticsThe 88E1116R device has two regulators to generateDownshift"mode for two-pair cable installationsall required voltages. The 88E1116R device can beFully integrated digital adaptive equalizers, echopowered by a single 1.8V, 2.5V, or 3. 3V supply Alternacancellers, and crosstalk cancellerstively, if the regulators are not used, then the 88E1116RAdvanced digital baseline wander correctiondevice can be powered by a 1. 8v and 1.2V supplyAutomatic MDi/MDIX crossover at all speeds ofThe 88E1116R device incorporates the Marvell@ VirtualoperationCable Tester (VCTTM)feature, which uses TimeAutomatic polarity correctionDomain Reflectometry(TDR)technology for the remotelEEE 802. 3u compliant Auto-Negotiationidentification of potential cable malfunctions, thusSoftware programmable LEd modes including LEDreducing equipment returns and service calls. UsingtestingVCT, the alaska 88E1116R device detects and reportspotential cabling issues such as pair swaps, pair polar-Supports IEEE 1149.1 JTAGity and excessive pair skew. The device will also detectMDC/MDIO Management Interfacecable opens, shorts or any impedance mismatch in theCRC checker, packet countercable and reporting accurately within one meter the disPacket generationtance to the faultVirtual Cable Tester(VCT)The 88E1116R device integrates MDI interface terminaAuto-Calibration for MAc Interface outputstion resistors into the Phy. this resistor integrationComa Mode supportfacilitates board layout and reduces board cost byRequires a single 1.8v supplyreducing the number of extenal components. The new10 pads can be supplied with 1.8V, 2.5V, or 3. 3VMarvell calibrated resistor scheme will achieve andexceed the accuracy requirements of the IEEE 802.3Two regulators generate all required voltagesRegulator can be supplied with 1.8V,2.5V or 3.3Vreturn loss specificationsCommercial gradeThe 88E1116R device supports the reduced gmll64-Pin QFN package(RGMI)for direct connection to a MAC/Switch portThe 88E1116R device uses advanced mixed-signal processing to perform equalization, echo and crosstalkcancellation, data recovery, and error correction at agigabit per second data rate. The device achievesrobust performance in noisy environments with very lowpower dissipationThe 88E 1116R device is offered in a 64-pin QFn pack-The 88E1116R device is footprint compatible with the88E1116 device As the 88E 1116R device employs integrated MDi interface terminations, all external mDIinterface termination resistors and capacitors must beremoved when migrating from the 88E1116 to88E1116R. See 88E1116 to 88E1116R Migration Appli-cation note for more detailsCopyright o 2007 MarvellCONFIDENTIALDoC. No. MV-S104224-00. Rev.March 1. 2007. AdvanceDocument Classification: Proprietary InformationPage 388E1116RMARVELLo Alaska Gigabit Ethernet TransceiverMagnMedia Types10/1001000Mbps88E1116R|a盖10BASEEthernet macRJ-45Device100BASE-TX1000BASE-TMAC InterfaceRGMII88E1116R Device used in Copper ApplicationDoc. No. MV-S104224-00. Rev.CONFIDENTIALCopyright o 2007 MarvellPage 4Document Classification: Proprietary InformationMarch 1. 2007. AdvanceTable of contentsSECTION 1. SIGNAL DESCRIPTION1.1 Pin Description101.1.1 Pin Type Definitions1264 Pin QFN Pin Assignment List- Alphabetical by Signal Name.……,…,,…,161.3 O State at Various Test or reset modes .mmm.,17SECtION 2. FUNCTIONAL SPECIFICATIONS2.1 Copper Media Interface..国面画192.2 MAC Interface(RGMII)4192.2.1 10/100 Mbps Functionality2.2.2 TX ER and RX ER Codingaaaaaiiaia t23Lo。 pback……………,….….….,.,…….…,…,….….……,…….……………212.3.1 MAC Interface Loopback212.3.2 Line Loopback.222.3.3 EXternal Loopback24 Synchronizing F|FQ….…,,…,…,,,,,,…,,,,,…,,,…,,,,…,……242.5 Copper Media Transmit and receive Function.man..m日a252.5.1 Transmit side Network Interface252.5.2 Encoder2.5.3 Receive Side Network Interface2.5. 4 Decoder2.6 Regulators and Power Supplies282.6.1 AVDD2.6.2 AVDDC282.6.3 AVDDR292.6.4 AVDDX2.6.5DVDD…292.6.6 VDDO26.7 VDDOR.292.7 Power Management302.7.1 Low Power Modes2.72 Low Power Operating Modes……2.7.3 RGMl Effect on Low Power modes3228Auto- Negotiation.........……33Copyright o 2007 MarvellCONFIDENTIALDoC. No. MV-S104224-00. Rev.March 1. 2007. AdvanceDocument Classification: Proprietary InformationPage 588E1116RMARVELL Alaska Gigabit Ethernet Transceiver2.9 Downshift Feature…352.10 Advanced virtual Cable Tester362.10.1 Maximum Pe2.10.2 First Peak372.10.3 Offsetp2. 10. 4 Sample Poin2.10.5 Pulse Amplitude and Pulse Width392. 10.6 Drop Link...392.10.7 VCTTM With Link Up392.11 Data Terminal Equipment (DTE)Detect........2.12 CRC Error Counter and frame Counter412.12. 1 Enabling the crc error counter and frame counter.412.13 Packet generator412.14 MDI/MDIX Crossover422.15P。 olarity Correction..…432.16LED,,,,,,,,,,,…,…,,442.16.1 LED Polarity452.16.2 Pulse Stretching and Blinking.462. 16.3 Bi-Color LED Mixing472.16.4 Modes of Operation482.17 EEE 1149.1 Controller522.17.1 BYPASS Instruction522.17.2 SAMPLE/PRELOAD Instruction.52217.3 EXTEST Instruction552,17.4 The clamP Instruction552,17.5 The high-z Instruction552.17.6 ID CODE Instruction552.18 Interrupt.552.19 Automatic and Manual Impedance Calibration.……,…,…,…,…,…,…,……562. 19. MAC Interface calibration circuit562.19.2 MAC Interface Calibration Register Definitions2. 19.3 Changing Auto Calibration Targets2. 19. 4 Manual Settings to The Calibration Registers“““582.20 Configuring the 88E1116R Device..2.20. 1 Hardware Configuration612.20.2 Software Configuration-Management Interface632.21 Temperature sensor64Doc. No. MV-S104224-00. Rev.CONFIDENTIALCopyright o 2007 MarvellDocument Classification: Proprietary InformationMarch 1. 2007. AdvanceSECTION 3 REGISTER DESCRIPTION65SECTION 4, ELECTRICAL SPECIFICATIONS1104.1. Absolute Maximum Ratings,…,…,…,…,,…,…,…,…,…,…,,…,…,……,1104.2. Recommended Operating Conditions..,,.,……,,……1114.3. Package Thermal Information.………….……….…………1124.3.1 Thermal Conditions for 64-pin QFn Package1124. 4. Current Consumption...........面量量…1134.4.1 Current Consumption AVDD..1134.4.2 Current Consumption AVDDC..1134.4.3 Current Consumption AVDDR1144.4.4 Current Consumption AVDDX1144.4.5 Current Consumption DVDD4.4.6 Current Consumption VDDo1154.4.7 Current Consumption VDDOR1154.4.8 Current Consumption Center Tap1154.5. DC Operating Conditions1164.5.1 Non-RGMlI Digital Pins1164.5.2 Internal resistor Description4.5.3 Stub-Series Transceiver LogIc (55/.21174.5 4 EEE DC Transceiver Parameters1194.6. AC Electrical Specifications1204.6.1 Reset Timing ..1204.6.2 XTAL IN/XTAL OUT Timing1214.6.3 LED to CONFIG Timing1214.7 RGMII Interface Timing……,,…1224.7.1 RGMl AC Characteristics4.7.2 RGMII Delay Timing for different RGMiI Modes1234.8. MDC/MDIO Timing…12549. JTAG Timing…,,…1264.10.EEE AC Transceiver parameters1274.11. Latency Timing........….…1284.11.1 RGMII to 1000BASE-T Transmit Latency Timingaa“aa1284.11.2 RGMII to 100BASE-TX Transmit Latency Timing1284.11.3 RGMiI to 10BASE-T Transmit Latency Timing4. 11. 4 1000BASE-T to RGMll Receive Latency Timing1304. 11.5 100BASE-TX to RGMII Receive Latency Timing.1304.11.610 BASE-T to RGMll Receive Latency Timing……….….…………,130SECTION 5. PACKAGE MECHANICAL DIMENSIONS1315.1 64-Pin QFN Package...131Copyright o 2007 MarvellCONFIDENTIALDoC. No. MV-S104224-00. Rev.March 1. 2007. AdvanceDocument Classification: Proprietary InformationPage 788E1116RMARVELL Alaska Gigabit Ethernet TransceiverSECTION 6. ORDER INFORMATION1336.1 Ordering Part Numbers and Package Markings1336.1.1 RoHS 5/6 Marking Example1346.1.2 RoHS 6/6 Marking Example135Doc. No. MV-S104224-00. Rev.CONFIDENTIALCopyright o 2007 MarvellPage 8Document Classification: Proprietary InformationMarch 1. 2007. AdvanceSignal DescriptionSection 1. Signal DescriptionThe 88E1116R device is a 10/100/1000BASE-T Gigabit Ethernet transceiverFigure 1: 88E1116R Device 64-Pin QFN Package(Top view)文gg9廿廿廿廿廿廿凵廿廿廿凵廿守令导好寸守哥导$85#將RX CTRL4932TSTPTRXDIO5031MDIPIORXD[51EPAD-VSS30d MDIN[O]VDDOR52290 AVDDRX CLK5328叫NCRXD[2]54AVDDRXD]5526MD|P[1VDDOR56VREF57MARVEL L③24E MDIP[2TXD0]□5823MDIN[2TXD[1]B5988E1116R22AVDDTX_CLK F6021AVDDTXD[2Top ViewMDIP[3TXD3]□62190 MDIN[3]TⅩCTRL6318□NCCONFIG[O]64CTRL18三s回口cc×O百口口艺艺安安Copyright o 2007 MarvellCONFIDENTIALDoc. No. MV-S104224-00 RevMarch1.2007. AdvanceDocument Classification: Proprietary InformationPage 988E1116RMARVELL. Alaska Gigabit Ethernet Transceiver1.1 Pin Description1.1.1 Pin Type DefinitionsPin Ty peDefinitionHInput with hysteresisVOInput and outputInput onlOutput onlPUIntemal pullPDInternal pull downOpen drain outputTri-state outputADC sink capabilityDoC. No. MV-S104224-00 RevCONFIDENTIALCopyright o 2007 MarvellPage 10Document Classification: Proprietary InformationMarch.2007. Advance
- 2020-12-03下载
- 积分：1
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Camshift目标跟踪matlab实现
matlab实现的Camshift目标跟踪算法。
- 2020-11-06下载
- 积分：1
