acx735_usb_ddr3_tft

代码说明：

说明：  USB传图至fpga板缓存至DDR内，FPGA再读出图像数据，显示在TFT彩屏上；(USB to the FPGA board cache DDR, FPGA read out the image data, display on the TFT color screen;)

文件列表：

usb_ddr3_tft\bit\usb_ddr3_tft.bit, 2192120 , 2019-09-30
usb_ddr3_tft\ddr3_pin_.ucf, 5808 , 2019-05-26
usb_ddr3_tft\usb_ddr3_tft.srcs\constrs_1\new\usb_ddr3_tft.xdc, 6301 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\datasheet.txt, 2849 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\docs\phy_only_support_readme.txt, 610 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\par\example_top.xdc, 1277 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\par\readme.txt, 860 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\rtl\example_top.v, 32058 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v4_2_axi4_tg.v, 18550 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v4_2_axi4_wrapper.v, 33395 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v4_2_cmd_prbs_gen_axi.v, 10316 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v4_2_data_gen_chk.v, 7249 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen\mig_7series_v4_2_tg.v, 27431 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\sim\ddr3_model.sv, 170147 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\sim\ddr3_model_parameters.vh, 278877 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\sim\ies_run.sh, 5694 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\sim\readme.txt, 10158 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\sim\sim.do, 6936 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\sim\sim_tb_top.v, 25101 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\sim\vcs_run.sh, 5338 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\sim\wiredly.v, 5614 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\sim\xsim_files.prj, 17773 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\sim\xsim_options.tcl, 3266 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\sim\xsim_run.bat, 3399 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\mig.prj, 8642 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\user_design\rtl\mig_7series_0_mig_sim.v, 76597 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0.veo, 9546 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0.xci, 369813 , 2019-09-29
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0.xml, 6293358 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0_xmdf.tcl, 24779 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_a.prj, 8642 , 2019-09-29
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\xil_txt.in, 1218 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\xil_txt.out, 161 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\pll\pll.xci, 97578 , 2019-09-29
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\pll\pll.xml, 290113 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\rd_ddr3_fifo\rd_ddr3_fifo.xci, 74706 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\rd_ddr3_fifo\rd_ddr3_fifo.xml, 571973 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\usb_fifo\usb_fifo.xci, 74221 , 2019-09-29
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\usb_fifo\usb_fifo.xml, 571609 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\wr_ddr3_fifo\wr_ddr3_fifo.xci, 74710 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\wr_ddr3_fifo\wr_ddr3_fifo.xml, 571971 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\new\define\define.v, 42 , 2019-09-20
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\new\fifo2mig_axi.v, 10797 , 2019-09-29
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\new\tft_ctrl\tft_ctrl.v, 4547 , 2019-09-29
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\new\tft_ctrl\tft_timing_parameter.vh, 981 , 2019-09-20
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\new\usb_ddr3_tft.v, 19963 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\new\usb_stream_out.v, 2970 , 2019-09-29
usb_ddr3_tft\usb_ddr3_tft.xpr, 11620 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\rtl\traffic_gen, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\par, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\rtl, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\sim, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design\synth, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\user_design\rtl, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\docs, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\example_design, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0\user_design, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\mig_7series_0, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0\_tmp, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\mig_7series_0, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\pll, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\rd_ddr3_fifo, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\usb_fifo, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip\wr_ddr3_fifo, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\new\define, 0 , 2019-09-29
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\new\tft_ctrl, 0 , 2019-09-29
usb_ddr3_tft\usb_ddr3_tft.srcs\constrs_1\new, 0 , 2019-09-29
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\ip, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1\new, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs\constrs_1, 0 , 2019-09-29
usb_ddr3_tft\usb_ddr3_tft.srcs\sources_1, 0 , 2019-09-29
usb_ddr3_tft\bit, 0 , 2019-09-30
usb_ddr3_tft\usb_ddr3_tft.srcs, 0 , 2019-09-30
usb_ddr3_tft, 0 , 2019-09-30
图片素材\001.bin, 768000 , 2019-09-29
图片素材\001.bmp, 1152054 , 2019-09-29
图片素材\001s.bin, 768000 , 2019-09-30
图片素材\002.bin, 768000 , 2019-09-29
图片素材\002.bmp, 1152054 , 2019-09-29
图片素材\003.bin, 768000 , 2019-09-29
图片素材\003.bmp, 1152054 , 2019-09-29
图片素材, 0 , 2019-09-30