MicroElectronic Circuit Design
微电子电路设计第五版,Richard C. Jaeger, Traveis N. Blalock编著。FIETH EDITIONMICROELECTRONICHM-M- CIRCUIT DESIGNRICHARD C. JAEGERAuburn UniversityTRAVIS N. BLALOCKUniversity of VirginiaMcGrawEducationGrawEducationMICROELECTRONIC CIRCUIT DESIGN. FIFTH EDITIOPublished by McGraw-Hill Education, 2 Penn Plaza, New York, NY 10121 CopyrightC 2016 by McGraw-Hill EducationAll rights reserved. Printed in the United States of America. Previous editions 2011, 2008, and 2004. No part of thispublication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system,without the prior written consent of McGraw-Hill Education, including, but not limited to, in any network or otherelectronic storage or transmission, or broadcast for distance learninSome ancillaries, including electronic and print components, may not be available to customers outside the United StatesThis book is printed on acid-free pape1234567890DOw/DOw1098765ISBN978-0-07-352960-8MHID0-07-352960-5sident Products markets Kurt LVice President, General Manager, Products Markets: Marty Langece President, Content Design Delivery: Kimberly Meriwether DavidManaging director: Thomas TimpGlobal Publisher Raghu srinivasanDirector. Prodrelopment: RoDirector, Digital Content Development: Thomas Scaife, Ph DProduct develoVincent brashMarketing manager: Nick Mc faddenDirector, Content Design Delivery: Linda avenariusProgram meSchillingContent Project Managers: Jane Mohr, Tammy Juran, and Sandra M. SchneeBuyer: Jennifer PickelDesign: Studio Montage, St Louis, MOContent Licensing Specialist: DeAnna DausenerCompositor: MPS LimitedPrinter.R. DonnellAll credits appearing on page or at the end of the book are considered to be an extension of the copyright pageLibrary of Congress Cataloging-in-Publication DataJaeger. Richard cMicroelectronic circuit design/Richard C. Jaeger, Auburn University,Travis N. Blalock, University of Virginia. --Fifth editionpages cmIncludes bibliographical references and indexISBN978-0-07-352960-8(alk. paper)-ISBN0-07-338045-8(alk. paper)d 1. Integrated circuits--Design and construction. 2. Semiconductors--Design and construction. 3. Electronic circuitesign. I. Blalock, Travis N. Il. TitleTK7874.J3332015621.3815-dc232014040020The Internet addresses listed in the text were accurate at the time of publication. The inclusion of a website does not indicatean endorsement by the authors or McGraw-Hill Education, and McGraw-Hill Education does not guarantee the accuracy ofthe information presented at these siteswww.mhhe.comTOTo Joan, my loving wife and life long partnerRichard C. JaegerIn memory of my father, Professor Theron vaughnBlalock, an inspiration to me and to the countlessstudents whom he mentored both in electronicdesign and in life.Travis n blalockBRIEF CONTENTSPreface xxChapter-by-Chapter Summary XXV12 Operational Amplifier Applications 685PART ONE13 Small-Signal Modeling and LinearSOLID-STATE ELECTRONICS AND DEVICESAmplification 77014 Single-Transistor Amplifiers 8411 Introduction to Electronics 32 Solid-State Electronics 4115 Differential Amplifiers and Operational Amplifier3 Solid-state Diodes and Diode circuits 72Design 9524 Field-Effect Transistors 14416 Analog Integrated Circuit Design Techniques 10315 Bipolar Junction Transistors 21517 Amplifier Frequency Response 111318 Transistor Feedback Amplifiers andPART TWOOscillators 1217DIGITAL ELECTRONICSAPPENDICES6 Introduction to Digital Electronics 2837 Complementary MOS (CMOS) Logic Design 359A Standard Discrete Component Values 12918 MOS Memory Circuits 414B Solid-State Device Models and sPIce simulationParameters 12949 Bipolar Logic Circuits 455C TWo-Port Review 1299PART THREIndex 1303ANALOG ELECTRONICS10 Analog Systems and Ideal OperationalAmplifiers 51711 Nonideal Operational Amplifiers and FeedbackAmplifier Stability 587CONTENTSPreface xxCHAPTER 2Chapter-by-Chapter Summary XXVSOLID-STATE ELECTRONICS 41PART ONE2.1 Solid-State Electronic materials 432.2 Covalent bond model 44SOLID-STATE ELECTRONICS2.3 Drift Currents and mobility inAND DEVICES 1Semiconductors 472.3.1 Drift Currents 47CHAPTER 12.3.2 Mobility 48INTRODUCTION TO ELECTRONICS 32.3.3 Velocity Saturation 482.4 Resistivity of Intrinsic Silicon 491.1 A Brief History of Electronics: From2.5 Impurities in Semiconductors 50Vacuum Tubes to Giga-Scale Integration 52.5.1 Donor Impurities in silicon 511.2 Classification of Electronic Signals 82.5.2 Acceptor Impurities in Silicon 511.2.1 Digital signals 92.6 Electron and hole concentrations in1.2.2 Analog Signals 9Doped semiconductors 511.2.3 A/D and D/A Converters--Bridging2.6.1Type Material (ND >NA)52the analog and Digital2.6.2 p-Type Material (N,A>ND)53Domains 102.7 Mobility and Resistivity in Doped1.3 Notational conventions 12Semiconductors 541.4 Problem-Solving Approach 132.8 Diffusion currents 581.5 Important Concepts from Circuit2. 9 Total Current 59Theory 152.10 Energy Band Model 601.5.1 Voltage and current Division 152.10.1 Electron-Hole pair generation in1.5.2 Thevenin and norton circuitan intrinsic semiconductor 60Representations 162.10.2 Energy Band Model for a Doped1.6 Frequency Spectrum of ElectronicSemiconductor 61Signals 212.10.3 Compensated semiconductors 611.7 Amplifiers 222.11 Overview of Integrated circuit1.7.1 Ideal operational amplifiers 23Fabrication 631.7.2 Amplifier Frequency Response 25Summary 661.8 Element Variations in Circuit Design 26Key Terms 671.8.1 Mathematical modeling ofReference 68Tolerances 26Additional Reading 681.8.2 Worst-Case Analysis 27Problems 688.3 Monte Carlo analysis 291.8.4 Temperature Coefficients 32CHAPTER 31.9 Numeric Precision 34SOLID-STATE DIODES AND DIODE CIRCUITS 72Summary 34Key Terms 353.1 The pn Junction Diode 73References 363.1.1 pn Junction Electrostatics 73Additional Reading 363.1.2 nternal diode currents 77Problems 363.2 The i-v Characteristics of the diode 78VIllContents3.3 The Diode Equation: A Mathematica3.15 Full-Wave Bridge Rectification 123Model for the diode 803.16 Rectifier Comparison and Design3.4 Diode Characteristics under reverse, ZeroTradeoffs 124and forward bias 833.17 Dynamic Switching Behavior of the Diode 1283.4.1 Reverse bias 833.18 Photo diodes, solar cells, and3. 4.2 Zero bias 83Light-Emitting Diodes 1293.4.3 Forward Bias 843.18.1 Photo diodes and3.5 Diode Temperature Coefficient 86Photodetectors 1293.6 Diodes under reverse bias 863.18.2 Power Generation from Solar Cells 1303.6.1 Saturation Current in real3.18. 3 Light-Emitting Diodes(LEDs)13Diodes 87Summary 1323.6.2 Reverse Breakdown 89Key Terms 1333.6.3 Diode model for the breakdownReference 134Region 90Additional Reading 1343.7 pn Junction Capacitance 90Problems 1343.7.1 Reverse bias 903.7.2 Forward Bias 91CHAPTER 43.8 Schottky Barrier Diode 933.9 Diode SPICE Model and layout 93FIELD-EFFECT TRANSISTORS 1443.9.1 Diode Layout 944.1 Characteristics of the MOS Capacitor 1453.10 Diode Circuit Analysis 954.1.1 Accumulation Region 1463.10.1 Load-Line Analysis 964.1.2 Depletion Region 1473.10.2 Analysis Using the Mathematical4.1.3 Inversion Region 147Model for the diode 974.2 The nmos transistor 1473.10.3 The Ideal diode model 1014.2.1 Qualitative i-v Behavior of the3.10.4 Constant Voltage Drop Model 103NMOS Transistor 1483.10.5 Model Comparison and4.2.2 Triode Region Characteristics ofDiscussion 104the nmos transistor 1493.11 Multiple-Diode Circuits 1054.2.3 On Resistance 1523.12 Analysis of Diodes Operating in the4.2.4 Transconductance 153Breakdown Region 1084.2.5 Saturation of the i-v3.12.1 Load-Line Analysis 108Characteristics 1543.12.2 Analysis with the Piecewise4.2.6 Mathematical model in theLinear model 108Saturation (Pinch-off)3.12.3 Voltage regulation 109Region 1553.12.4 Analysis Including Zener4.2.7 Transconductance in saturation 156Resistance 1104.2.8 Channel-Length Modulation 1563.12.5 Line and Load Regulation 1114.2.9 Transfer characteristics and3.13 Half-Wave Rectifier Circuits 112Depletion-Mode MosFETs 1573.13.1 Half-Wave Rectifier with resistor4.2.10 Body Effect or SubstrateLoad 112Sensitivity 1593.13.2 Rectifier Filter Capacitor 1134.3 PMOS Transistors 1603.13.3 Half-Wave Rectifier with rc load 1144.4 MOSFET Circuit Symbols 1623. 13.4 Ripple Voltage and Conduction4.5 Capacitances in MOS Transistors 165Interval 1154.5.1 NMOs Transistor Capacitances in3.13.5 Diode Current 117the Triode region 1653.13.6 Surge Current 1194.5.2 Capacitances in the Saturation3.13.7 Peak-Inverse-Voltage(PlV)Rating 119Region 1663.13.8 Diode Power Dissipation 1194.5.3 Capacitances in Cutoff 1663.13.9 Half-Wave Rectifier with Negative4.6 MOSFET Modeling in SPICE 167Output Voltage 1204.7 MOS Transistor Scaling 1683.14 Full-Wave Rectifier Circuits 1224.7.1 Drain Current 1693. 14.1 Full-Wave Rectifier with Negative4.7.2 Gate Capacitance 169Output Voltage 1234.7.3 Circuit and power densities 169ContentsIX4.7.4 Power-Delay Product 1705.3 The pnp Transistor 2234.7.5 Cutoff Frequency 1705.4 Equivalent Circuit Representations for the4.7.6 High Field Limitations 171Transport Models 2254.7.7 The unified mos transistor model5.5 The i-v Characteristics of the bipolarIncluding High Field Limitations 172Transistor 2264.7.8 Subthreshold conduction 1735.5.1 Output Characteristics 2264.8 MOs Transistor Fabrication and layout5.5.2 Transfer characteristics 227Design Rules 1745.6 The Operating Regions of the Bipolar4.8.1 Minimum Feature size andTransistor 227Alignment Tolerance 1745.7 Transport Model Simplifications 2284.8.2 Mos Transistor Layout 1745.7.1 Simplified Model for the Cutoff4.9 Biasing the NMOS Field-EffectRegion 229Transistor 1785.7.2 Model Simplifications for the4.9.1 Why Do We Need Bias? 178Forward-Active Region 2314.9.2 Four-Resistor Biasing 1805.7.3 Diodes in Bipolar Integrated4.9.3 Constant Gate-Source VoltageCircuits 237Bias 1845.7.4 Simplified Model for the4.9.4 Graphical analysis for theReverse-Active Region 238Q-Point 1845.7.5 Modeling Operation in the4.9.5 Analysis Including Body Effect 184Saturation Region 2404.9.6 Analysis Using the Unified5.8 Nonideal Behavior of the bipolarModel 187Transistor 2434.10 Biasing the PMos Field-Effect Transistor 1885.8.1 Junction Breakdown Voltages 2444.11 The junction Field-Effect Transistor5.8.2 Minority-Carrier Transport in theUFET190Base Region 2444.11.1 The JFET With Bias Applied 195.8.3 Base Transit time 2454.11.2 JFET Channel with Drain-Source5.8.4 Diffusion Capacitance 247Bias 1935.8.5 Frequency Dependence of the4.11.3 n-Channel jfet i-v Characteristics 193Common-Emitter current gain 2484.11.4 The p-Channel JFET 1955.8.6 The Early Effect and Early4.11.5 Circuit Symbols and JFET ModelVoltage 248Summary 1955.8.7 Modeling the Early Effect 2494.11.6 JFET Capacitances 1965.8.8 Origin of the Early Effect 2494.12 JFET Modeling in Spice 1965.9 Transconductance 2504.13 Biasing the JFET and Depletion-Mode5.10 Bipolar Technology and sPiCe Model 251MOSFET 1975.10.1 Qualitative Description 251Summary 2005.10.2 SPICE Model Equations 252Key Terms 2025.10.3 High-Performance BipolarReferences 202Transistors 253Problems 2035.11 Practical bias circuits for the bjt 2545.11.1 Four-Resistor bias network 256CHAPTER 55.11.2 Design Objectives for theBIPOLAR JUNCTION TRANSISTORS 215Four-Resistor bias network 2585.11.3 terative Analysis of the5.1 Physical Structure of the BipolarFour-Resistor bias circuit 262Transistor 2165.12 Tolerances in bias circuits 2625.2 The Transport Model for the npn5. 12.1 Worst-Case Analysis 263Transistor 2175. 12.2 Monte Carlo Analysis 2655.2.1 Forward Characteristics 218Summary 2685.2.2 Reverse Characteristics 220Key Terms 2705.2.3 The Complete Transport ModelReferences 270Equations for Arbitrary BiasProblems 271Conditions 221
- 2020-12-10下载
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STM32移植到GD32的注意事项
GD32的性价比和稳定性都很高。我更喜欢用GD32.。但不是100%兼容的。需要注意一些细节。2.内部 Flash1)芯片设置读保护用法描述由于GD的Fash是自己的专利技术,STM的Fash是第三方提供的,所以GD的 Flash和STM的Fash有些许差异。GD的擦除时间会长一点解决方法在写完KEY序列以后,需要读该位,确认key已生效。所以,这里应该插入While(! (FLASH->CR &0x200);//Wait OPTWRE或可简单插入两个NOPNOPONOPO在ST库中,只有FLASH Status FLaSH Erase Option Bytes(void)FLaSH Status FlaSH ProgramOption Byte Data(uint32 t Address, uint8 t DataFLASH Status FLASH_ Enable WriteProtectionuint32 t FLASH PagesFLASH Status FLASH ReadOutProtection (Functional State New State)四个函数需要修改。2)IAP在应用中编程描述GD32由于有fash的0访问时序,同SM32在Fash的Ease和 Program上存在差别,GD32的 Erase和 Program时间比STM32的稍微长些建议对 Erase和 Progran时间进行修改解决方法将宏定义井 define erase timeout(luint32 t)OX000B000O)#define ProgramTimeout(uint32_t)ox00002000修改为:#define erasetimeout((uint32_t)OX00OFFFFF#define ProgramTimeout(uint32 t)OxOOOOFFFF备注: Erase和 Program时间宏定义在stm3210 x flash. c源文件中路径: braiesSTM32F10 x Std Periph Driversr)3)用IAR下载配置解决方法在批量牛产的时候首先会烧写一个USB的boot,这个boot自动运行后在由上位机软件进行烧写应用程序。如果boot程序不能自动运行则需要重新插拔次电源。给生产造成一些麻烦。产生不能自动运行程序的原因是如果程序设置读保护的话需要等待 FLASH CR的第9[ OPTWRE]位为1.如果没有置位的话继续执行就会出错。由」ST的执行速度慢,程序执行到读 FLASH CR寄存器的时候该位已经置1,GD的执行速度比较快,程序运行到这的时候该位还没置1,因此需要在 FLASH ReadOut Protection函数里面添加一些轮询该位为1或者加延时3.ISP烧写软件1)ISP烧写,建议使用官方烧写软件性述芯片内部同有区别解决方法建以到下载最新版本的另外也有专门的烧写软件(可以到论坛下毂如果使用自制的软件或脱机编程器,实现和完全兼容,建议修改以下参数。页擦除等待超时时间增加至整片擦除等待超时时间增加至左右字编程等待超时时间增加至,臾编程等笭超时时间增加至I/0日1)I0口外部中断使用方法措述在关闭期间,如果外部引脚有电平的变化,在使用MR打开中断后会马上进入中断服务程序。理论是打开中断前,不管管脚是否有电平的变化,都不会影响到打开后的中断响应。解决方法所以解决方法就是通过禁用上升沿或者下降沿检测寄存器来开关中断,不能使用IMR屏蔽奇存器。程序如下关闭沿检测,以达到关闭中断的目的,下降沿使用寄存器,上升沿使用寄存器2)在待机模式,PA8引脚特殊设置描述在使用低功耗的情况下,PA8会被MCU在内部被设置为地PA8复用为MU内部频率输出,超低功耗设时需要悬空解决方法在待机模式,PA8悬空不用3)低功耗下必须注意描述在使用低功耗情况下,把软件全部端口(AF)时钟关掉,无论是否有该端凵。4)当有脉冲群冲击管脚摧述需要在在进入中断后关闭中断4.定时器1)定时器输入捕获模式需要软件清中断描述sTM定吋时器输入捕获模式默认能硬件清中断,GD为了更加严格要求配置,需要做软件清中断解决方法软件清除标志位2)定时器向上脉冲计数模式设置述定时器的用法差异解决方法脉冲计数模式下,装载值必须设置为比预期值大,否则不计数在ST上如果重载值不设置(初始为0)的时候,CNT可以正常计数。在GD上如果重载值不设置保持初始为0的时候,会因为重载值为零,即便是来一个脉冲也会导致所有的寄存器复位从而不能正常计数。型号GD32F1系列MCUF|ah256B8及以上的型号)3)TIM、ADC模块描述Tmer、ADC模块的触发信号宽度要求解决方法|由于内部有高速和低速两条外围总线,Tmer、ADC模块和其他外设共同使用这两个总线。GD32F103/101系列Fash128KB及以下的型号, Timer、ADC等模块识別触发信号的条件是触发信号宽度大于模块所在总线的时钟宽度5.串口 USART1) USART连续发送数据字节有空闲位带述字节间有空闲位解决方法|对于一般的通讯米说,不会有影响,只对于一般在通讯上有特殊协议的,才会产生数据不准确的情况所以,特定情况,修改程序6.I2C总线1)硬件L2C特殊配置述GD的C相对STM的来说要少一个标志位解决、宏地址定义改交方法2、硬件I2C在会在向从机发送7bits地址完成后,从札还没来得及识别。(看客户应用)我们可以在发送完7bits后加个延时,让从机完全识别I2C Send7bitAddress(I2C1, EEPROM ADDRESS, I2C Direction TransmitterintOfffhile(i --3、检测ADDR不能使用I2 C Checkevent函数,因为他会清除ADR,可以使用I2 C Get FlagStatus函数就是把while(! I2C CheckEvent(I2C1I2C EVENT MASTER TRANSMITTER MODE SELECTED))Ey while(! I2C GetFlagStatus(I2C1, I2C FLAG ADDR))4、还有个关于编程步骤的严谨性,跟STW想比,我们是先 Clcar ack,再 Clear Arrd。7.ADC采集1)ADC采样设置述ADC启动解决方法|分三个方面时写入后,需要等待一段时间,如果用库的话就在 ADC CMD后面加20us左右的延付如果采用中断获得采样数据后,需要软件清除中断。8. SDio1) SDIO DAT3pin的在1 bit bus mode和4 bit bus mode下的配置摧述1、SD|O在1 bit bus mode下,DAT3pin是低电平,这样会导致 SD Card进入SP!模式。原因:初始化失败的原因主要是因为GD32的芯片SDO的DAT3∏存在BUG2、在4位模式下,通过上面的方法,程序能止常初始化,但不能正常读写SD卡原因:因为DAT3∏在前面已经配置成推挽输出,所以在4位模式下,不危正常读下。在调用4位模式前,把DAT3的端凵配置成复用推挽输入即可解决问题解决方法「1、1 bit bus mode的解决方法:建议在使能之前,先把配置成推挽输出,)且要置成高电平,使保持高电平即可2、4 bit bus mode的解决方法:在调用4位模式前,把DAT3的端口配置成复用输出即可解决问题。2)程序在刚烧完后能正常读写SD卡,断电再上电后,SD卡初始化失败,需要手动复位一次后才正常描述在某些SD卡中,GD32断电再上电,会引起SD卡上的时钟信号不正常,导致SD卡发送命令失败。解决方法在程序中,打开时钟后,增加一小段延时,以保证下时钟信号稳定。这个延时添加的地方:在即的配置文件中,然后在这个函数中找到就在这个后面加个延时。10. USBA, USB OTG1)客户使用的原工程时需要注意几点解|1、在中,增加如下图红色字体语句for (1=0; 18; i++) EPli= GetEndPoiNT(i)for(i=0:iregs. HC REGS [num]->HCCHAR, hcchar d3 2)pdev->host hc Status =HC NAK而V2.1.0版本的NAK处理过程如下else if (hcint b nak)if(hcchar b. eptype = EP TYPE_ INTR)UNMASK HOST INT CHH(num)USB OTG HC Halt(pdev, numelse if ((hcchar. b. eptype = EP TYPE CTRL)(hcchar b eptype = EP_ TYPE BULK))A re-activate the channel *hcchar, b chen =1hcchar b chris =0USB OTG WRITE REG32(&pdev->regs. HC REGS [num]->HCCHAR, hcchar d32)pdey->host HC Status [num]=HC_NAKCLEAR HC INT(hcreg, nak)唯一的区别就是 CLEAR HC INT( here,nak)的位置,在Ⅵ1.0.0版本中对于CTRL和BUK端点的NAK中断没有清除NAK,我们的芯片会因此产生多次IN传输的请求,导致数据传输错误。改为V2.1.1的写法后传输正常。(注意 HC Status在V2.1.0是数组,在Ⅵ1.0.0是单个数据,直接拷贝的话要去掉后面的[num])B.USB外设的工作频率有限制摧述有最低工作频率的要求,也就是APB1分频后的时钟必须大于12MHz,比如HCLK为56MHz,APB1的最大分频系数为4,56/4=14MHz,可以正常工作。11 SPI1)输入与输出配置要求(STM32不需要如此要求)解决丨GD32在使用SP时,o的配置必须严格遵守主从模式下的输入与输出配置,而方法STM32无此要求,相关代码如下主机模式下|o配置(主机以SP为例):GPIO InitStructure gPio Mode gPio Mode af plGPIO_ Init Structure GPIo Speed GPlO Speed 50MHzGPIO InitStructure. GPio Pin= GPlO Pin 5 GPIO Pin_ 7;GPIO Init(GPIOA, &GPIO InitstructureGPio Init Structure gPio Mode gPio Mode IN floating:GPio InitStructure gpio Pin gpio pin 6GPIO Init(GPIOA, &GPIO InitStructure)从机模式下o配置(从机以SP2为例)GPIo Init Structure GPio Mode gPlo Mode IN FloatingGPIO InitStructure GPIO Speed= GPl Speed 50MHzGPIO_InitStructure GPIO_ Pin GPIO Pin_13 GPIO_ Pin_15GPIO Init(GPIOB, &GPIO InitStructure)gPio Initstructure gpio mode gpio mode af pp.GPIO InitStructure. GPio Pin= GPIo Pin 14:GPIO_Init(GPIOB, &GPIO_Initstructure);3)在GD32的SP的时钟信号,空闲状态需要配置成高电平,以保证数据的稳定性,具体代码如下:红色字体代码解决SPI_ InitStructure SPl Direction =SPI_ Direction_ 2Lines fullDuplex;方法SPI InitStructure SPl Mode SPi Mode master.SPI Initstructure SPl Data Size= SPl Data Size 8bSPlInitStructure SPl_CPOL= SPI CPOL HighSPl Initstructure SPl CPHA= SPI CPHA 2EdgeSPI InitStructure SPI NSS= SPI NSS SoftSPI InitStructure SPl BaudRate Prescaler =SPI Baud Rate Prescaler 256:SPI Initstructure, Spi FirstBit= SPI FirstBit MSBSPI InitStructure SPl CRCPolynomial =7;SPl Init(sPl1, &SPl Initstructure);4)当作为从机时,在GD32中,时钟信号必须为8的整数倍。例如:红色字体代码解决SPI_InitStructure SPl_ Direction =SPl_ Direction_ 2Lines_ Full Duplex;方法SPI InitStructure. SPl Mode= SPl Mode MasterSPI InitStructure SPSPi Data Size 8SPl InitStructure SPl CPOL= SPI CPOL High;SPI Init Structure. SPl CPHA SPI CPHA_ 2EdgeSPI Initstructure SPl NSS= SPI NSs SoftSPI Initstructure Spl BaudRatePrescaler= SPl BaudRatePrescaler 256SPI InitStructure. SPl FirstBit= SPl First Bit MSBSPl Initstructure SPl CRCPolynomial =7;SPI Init(SPI1, &SPl InitStructure)5)在GD32中,不能使用SPLS_FLAG_BSY该位来判断SP总线数据是否接收或发送完成12.看门狗1)进入SToP模式前打开看门狗,通过RTc的ALR唤醒后,程序会不断被复位的现像摧述WDG内部有个 Reload信号,KEY奇器写AAA会使其拉高,过段时间自动拉低。在拉底之前进入STOP状态会使 Reload信号一直为高,等到退出SToP后也保持为高,之后再写AAAA没有办法让 Reload产生上升沿,也就没办法更新计数器了解决方法「进STOP之前不要 Reload,也可以调整下程序的顺序,把WwDG的配置放到RIC配置之前,效果是一样的。
- 2021-05-06下载
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