altera公司IP核使用手册.PDF
altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用A吉RAContentsChapter 1. About this MegaCore FunctionRelease informat1-1Device Family Support···Introduction.··········FeaturesOpen core plus evaluation1-3Performance···Chapter 2. Getting StartedDesign Flow衡·鲁·,看·,音番2-1Megacore Function walkthrough2-2Create a New quartus II Pi2-2Launch the mega Wizard Plug-in ManagerStep 1: Parameterize2-5Step 2: Set Up SimulationStep 3: Generate..,2-11Simulate the design2-13Compile the design2-13Pa Device2-14Set Up Licensing2-15ppend the license to yourdat file2-15Specify the License File in the Quartus II Software...2-15Example Simulation and Compilation..2-16Example quartus Ii project2-16Example simulation with Test Vectors,,,,,,2-16Chapter 3. SpecificationsyperTransport Technology Overview1HT SyStems3-2HT Flow ControlHyper Transport MegaCore Function SpecificationPhysical InterfaceSynchronization and alignment ...Protocol interfClocking Options.......HyperTransport Mega Core Function Parameters and HT Link Performance3-10Signals3-14CSR Module...3-31OpenCore plus time-Out BehaviorAppendix A. ParametersIntroduction鲁鲁鲁A-1Parameter listsDevice Family and Read Only registers···········,,,,,,,,,,A-1Base Address Registers番鲁,A-2Clocking OptionsA-3Advanced settingso March 2009 Altera corporationHyperTransport MegaCore Function User GuideAppendix B. Stratix Device Pin AssignmentsIntroductionB-1GuidelinesAppendix C. Example designGeneral descriptionAdditional informationRevision historyInto-lHow to Contact alteraInfo-1Typographic Conventions ..........Info-2Hyper Transport MegaCore Function User Guideo March 2009 Altera CorporationA吉RA1. About this MegaCore FunctionRelease InformationTable 1-1 provides information about this release of the Hyper Transport Mega CoretfunctioTable 1-1. Hyper Transport Mega Core Function Release InformationitenlDescription∨ ersion9.0Release dateMarch 2009Ordering codeIP-HTProduct ID(s)0098Vendor iD(s)6AF7Altera verifies that the current version of the quartus@ll software compiles theprevious version of each MegaCore function. Any exceptions to this verification arereported in the Mega Core lP Library release Notes and Errata. Altera does not verifycompilation with Mega Core function versions older than one releaseDevice Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families:Full support means the Mega Core function meets all functional and timingrequirements for the device family and may be used in production designsa Preliminary support means the Mega Core function meets all functionalrequirements, but may still be undergoing timing analysis for the device family;itmay be used in production designs with cautionTable 1-2 shows the level of support offered by the Hyper Transport MegaCorefunction for each of the altera device familiesTable 1-2. Device Family SupportDevice FamilySupportHard Copy Stratix@FullStratixFulStratix IIFulStratix‖GXPreliminaryStratix GXOther device familiesNo supportC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide1-2Chapter 1: About this MegaCore FunctionIntroductionIntroductionThe Hyper Transport Mega Core function implements high-speed packet transfersbetween physical(PhY) and link-layer devices, and is fully compliant with theHyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allowsdesigners to interface to a wide range of Hyper TransportTm technology(hT)enableddevices quickly and easily, including network processors, coprocessors, videochipsets, and ASICsFeaturesThe Hyper Transport Mega Core function has the following features8-bit fully integrated hT end-chain interfacePacket-based protocolDual unidirectional point-to-point linksUp to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction)200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devicesLow-swing differential signaling with 100-Q2 differential impedanceHardware verified with Hyper fransport interfaces on multiple industry standardprocessor and bridge devicesFully parameterized mega core function allows flexible, easy configurationFully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GXevice famillesApplication-side interface uses the Altera AtlanticTM interface standardManages Hr flow control, optimizing performance and ease of useIndependent buffering for each HT virtual channelAutomatic handling of ht ordering rulesStalling of one virtual channel does not delay other virtual channels(subject toorderingFlexible parameterized buffer sizes, allowing customization depending onsystem requirementsUser interface has independent interfaces for the HT virtual channels, allowingindependent user logic designCyclic redundancy code(crc) generation and checking to preserve data integrityIntegrated detection and response to common HT error conditions■ CRC errorsEnd-chain errorsFully integrated HT configuration space includes all required configuration spaceregisters and HT capabilities list registersHyper Transport MegaCore Function User Guideo March 2009 Altera CorporationChapter 1: About this MegaCore FunctionPerformance32-bit and 64-bit support across all base address registers bars)automatically handles all csr space accessesVerilog HDL and VHdL simulation supportOpen Core Plus EvaluationWith the Altera free Open Core Plus evaluation feature, you can perform the followingSimulate the behavior of a mcgafunction(Altera MegaCore function or AMPPmegafunction) within your systema Verify the functionality of your design, as well as quickly and easily evaluate itssize and speedGenerate time-limited device programming files for designs that includeMegaCore functionsProgram a device and verify your design in hardwareYou only need to purchase a license for the Mega Core function when you arecompletely satisfied with its functionality and performance and want to take yourdesign to productiono For more information about Open Core Plus hardware evaluation using theHyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"onpage 3-40 and AN 320: Open Core Plus Evaluation of megafunctionsPerformanceThe Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 showtypical performance and adaptive look-up table (alut) or logic element (LE)usagefor the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, andStratix GX devices respectively, using the Quartus@ II software version 7.1Table 1-3 shows the maximum supported data rates in megabits per second(Mbps)by device family and speed gradeTable 1-3. Maximum Supported Hyper Transport Data Rates (Note 1)Speed GradeDevice Family-36Stratix ll GX devices 1000 Mbps 1000 Mbps 800 MbpsNA(2)N/A(2NA(2)Stratix devices1000 Mbps 1000 Mbps 800 Mbps N/A(2)NA(2)NA(2)Stratix devicesN/A(2N/A(2)00 Mbps 800 Mbps 600 Mbps400 MbpsFlip-Chip packagesStratix devicesNA(2)NA(2)NA(2)600 Mbps400 Mbps400 Mbps(Wire Bond packagesStratix GX devicesN/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2)Notes to table 1-3(1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face(2) Devices ot this speed grade are not ottered in this device familyC March 2009 Altera CorporationHyperTransport Mega Core Function User GuideChapter 1: About this MegaCore FunctionPerformanceTable 1-4 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix II and Stratix II GX devicesTable 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX DevicesParametersMemoryUserRXCombinationalHT Link InterfacePosted Non-Posted Response ClockingALUTSLogicfMAX(MHz) MAx(MHz)Buffers BuffersBuffers Option(12)Registers M4K M512 ( 3)3)Shared3.5005200120500125(4RX/TX/Ref35005200500Ref/x8Shared36005400160500>150RX/TXShared4.0006,00016150RX/TX16Shared4,1006,200500125(4)RX/TX/RefShared4.1006200500125(4Ref/TxShared4.2006400160150RX/TXNotes to table 1-4.Refer to " Clocking Options "on page 3-7 for more information about these options(2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200(3)Figures for -3 speed grade devices only(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided byTable 1-5 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix and Stratix GX devicesTable 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX DevicesUser Interface fmaxParametersUtilizationHT Link fMAX MHz)MHZ)RXRXSpeed GradePosted Non-Posted Response Clocking Option LEsM4KBuffers BuffersBuffers)(2 Blocks.5-66Shared rx/tx/ref1240010073)100734448888Shared Ref/Tx 7, 60014400400100{3)100(3)Shared rxtx7,90016400400>125>100Shared rxtx8.900125>100168Shared Rx/T×Ref9,400124004001003)100316Shared ref/ ix9.500144001003)10073)16Shared rx/x9.700400125Notes to table 1-5:(1)Refer to Clocking Options"on page 3-7 for more information about these options(2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES(3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by fourHyper Transport MegaCore Function User GuideC March 2009 Altera CorporationA吉RA2. Getting StartedDesign FlowTo evaluate the HyperTransport Mega Core function using the Open Core Plus feature,include these steps in your design flowObtain and install the HyperTransport Mega Core functionThe HyperTransport Mega Core function is part of the MegaCore IP Library, which isdistributed with the Quartus ii software and downloadable from the altera websitewww.altera.como For system requirements and installation instructions, refer to Quartus II InstallationLicensing for Windows and Linux Workstations on the Altera website atwww.altera.com/literature/lit-qts.ispFigure 2-1 shows the directory structure after you install the HyperTransportMegaCore function, where is the installation directory. The default installationWindows is C: altera ; on Linux it islopt/alteraFigure 2-1. Directory StructureInstallation directorypContains the Altera MegaCore IP Library and third-party IP coresalteraContains the Altera MegaCore IP LibrarycommonContains shared componentshtContains the Hyper Transport Hyper Transport Megacore function files and documentationdocContains the documentation for the Hyper Transport MegaCore functionlibContains encrypted lower-level design filesexampleContains the design example for the Hyper Transport Mega Core function2. Create a custom variation of the Hyper Transport Mega Core function3. Implement the rest of your design using the design entry method of your choice4. Use the IP functional simulation model to verify the operation of your designo For more information about Ip functional simulation models, refer to the SimulatingAltera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook5. Use the Quartus II software to compile your designC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide2-2Chapter 2: Getting StartedMega Core Function WalkthroughIg You can also generate an Open Core Plus time-limited programming file,which you can use to verify the operation of your design in hardware6. Purchase a license for the hypertransport Mega Core functionAfter you have purchased a license for the Hyper transport mega Core functionfollow these additional steps1. Set up licensing2. Generate a programming file for the Altera device(s)on your board3. Program the Altera device(s)with the completed designMegaCore Function WalkthroughThis walkthrough explains how to create a custom variation using the AlteraHyper Transport IP Toolbench and the Quartus II software, and simulate the functionusing an ip functional simulation model and the modelsim software when you arefinished generating your custom variation of the function, you can incorporate it intoⅴ our overall projectIe IP Toolbench allows you to select only legal combinations of parameters, and warnsou of any invalid configurationsIn this walkthrough you follow these stepsCreate a New Quartus II Projecta Launch the MegaWizard Plug-in Manager■Step1: Parameterizea Step 2: Set Up Simulation■Step3: Generate■ Simulate the designTo generate a wrapper file and Ip functional simulation model using default values,omit the procedure described in"Step 1: Parameterizeon page 2-5Create a New Quartus ll ProjectCreate a new Quartus II project with the New Project Wizard, which specifies theworking directory for the project, assigns the project name, and designates the nameof the top-level design entityTo create a new project, perform the following steps1. On the Windows Start menu, select Programs> Altera> Quartus II tostart the Quartus lI software. Alternatively, you can use the Quartus II Web editionsoftware2. In the Quartus II window, on the File menu, click New Project Wizard. If you didnot turn it off previously, the New Project Wizard Introduction page appears3. On the New Project Wizard Introduction page, click NextHyper Transport MegaCore Function User Guideo March 2009 Altera Corporation
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EM算法详细例子及推导
EM算法详细例子及推导数θ),那么对于上面的实验,我们可以计算出他们出现我们观察到的结果即0=(5,9,.8,4,7,20=(B,A,A,B,4)的概率函数P(X=x10),2z)⑨)就叫做θ的似然函数。我们将它对θ求偏导并令偏导数为0,就可以得到如的结果P(X=x0,=20))=(;P(z=A)3(1-P(z=A)2C10(1-64)10A(1-6C104(1-0(1-6B)C106n(1-6我们将这个问题稍微改变一下,我们将我们所观察到的结果修改一…下我们现在只知道每次试验有几次投掷出正面,但是不知道每次试验投掷的是哪个硬币,也就是说我们只知道表中第一列和第三列。这个时候我们就称Z为隐藏变量( Hidden variable),X称为观察变量( Observed variable)。这个时候再来估计参数θ4和θB,就没有那么多数据可供使用了,这个时侯的估计叫做不完整数据的参数估计。如果我们这个时候冇某种方法(比如,正确的猜到每次投掷硬币是A还是B),这样的话我们就可以将这个不完整的数据估计变为完整数据估计当然我们如果没有方法来获得更多的数据的话,那么下面提供了一种在这种不完整数据的情况下来估计参数θ的方法。我们用迭代的方式来进行:(1)我们先赋给θ一个初始值,这个值不管是经验也好猜的也好,反正我们给它一个初始值。在实际使用中往往这个初始值是有其他算法的结果给岀的,当然随机给他分配一个符合定义域的值也可以。这里我们就给定64=0.7,6B=0.4(2)然后我们根据这个来判断或者猜测每次投掷更像是哪枚硬币投掷的结果。比如对于试验1,如果投掷的是Δ,那么出现5个止面的概率为C10×0.75×(1-07)5≈0.1029:;如果投掷的是B,出现5个正面的概率为C105×0.43×(1-0.4)5≈0.2007;基于试验1的试验结果,可以判断这个试验投掷的是使币A的概率为0.10290.10290.2007)-0.389是B的概率为02007(0.1029+0.2007)06611。因此这个结果更可能是投掷B出现的结果(3)假设上一步猜测的结果为B,A,A,B,A,那么恨据这个猜测,可以像完整数据的参数仙计一样(公式2重新计算的值这样一次一次的迭代2-3步骤直到收敛,我们就得到了θ的估计。现在你可能有疑问,这个方法靠谱么?事实证明,它确实是靠谱的。期望最大化算法就是在这个想法上改进的。它在估计每次投掷的硬币的吋候,并不要确定住这次就是硬币A或者B,它计算岀来这次投掷的硬币是A的概率和是B的概率;然后在用这个概率(或者叫做Z的分布)来计算似然函数。期望最大化算法步骤总结如下:F步骤先利用旧的参数值〃计算隐藏变量Z的(条件)分布P(万=2|Xn2),然后计算logP(,X=m)的期望B(o(2,X=x)=∑∑P(Z=别X=)P(Z=X=x)其中θ是当前的值,而θ是上一次迭代得到的值。公式中已经只剩下θ一个变量了,θ是一个确定的值,这个公式或者函数常常叫做Q函数,用Q(6,6)来表示。M步骤极大化Q,往往这一步是求导,得到由旧的θ值′米计算新的θ值的公式aQ总结一下,期望最大化算法就是先根据参数初值估计隐藏变量的分布,然后根据隐藏变量的分布来计算观察变量的似然函数,估计参数的值。前者通常称为E步骤,后者称为M步骤3数学基础首先来明确一下我们的目标:我们的目标是在观察变量X和给定观察样本:1,x2,…,rn的情況下,极大化对数似然函数(=>nP(X2=x;)(5)其中只包含观察变量的概率密度函数P(X2=2)=∑P(X=n,=)这里因为参数θ的写法与条件概率的写法相同,因此将参数θ写到下标以更明确的表述其中Z为隐藏随机变量,{}是Z的所有可能的取值。那么6)=∑h∑P(X=x,z=2)∑h∑。Px=x这里我们引入了一组参数(不要怕多,我们后面会处理掉它的)a,它满足可能的;,0;∈(0,1和∑;a=1到这里,先介绍一个凸函数的性质,或者叫做凸函数的定义。∫(x)为凸函数,=1,2,…,m,A∈[0,1∑1A对∫(x)定义域中的任意n个m1,x2,…,xn有f(∑Aa)≤∑mf(xr)i=1对于严格凸函数,上面的等号只有在x1=2xn的时候成立。关于凸函数的其他性质不再赘述。对数函数是一个严格凸数。因而我们可以有下面这个结果0)=∑hn∑≥∑∑ah(X=2n,2=C现在我们根据等号成立的条件来确定a;即P(X=x,Z=2)C(10)其中c是一个与j无关的常数。因为∑,=1,稍作变换就可以得到P(X;=x;)现在来解释下我们得到了什么。c;就是Z=2;在X=x;下的条件概率戌者后验概率。求α就是求隐藏随机变量Z的条件分布。总结一下目前得到的公式就是)-∑∑P(Xi=i,Z(12)直接就极大值比较难求,EM算法就是按照下面这个过程来的。它就是大名鼎鼎的琴生( Jensen)不等式(1)根据上一步的θ来计算α,即隐藏变量的条件分布(2)极大化似然函数来得到当前的的估计3.1极大似然估计好吧,我觉得还是再说说极大似然估计吧。给定一个概率分布D,假设其概率密度函数为f,其中f带有一组参数6。为了估计这组参数6,我们可以从这个分布中抽出一个具有n个采样值的X1,X2,…,Yn,那么这个就是n个(假设独立)同分布随机变量,他们分别有取值x1,x2…,xn,那么我们就可以计算出出现这样一组观察值的概率密度为lI f(ai)(13)对于f是离散的情况,就计算出现这组观察值的概率10)注意,这个函数中是含有参数0的。0的极大似然估计就是求让上面似然函数取极大值的时候的参数O值。般来说,会将上面那个似然函数取自然对数,这样往往可以简化计算。记住,这样仅仅是为了简化计算。取了自然对数之后的函数叫做对数似然函数。ln()=∑lnf(n)因为对数是一个严格单调递增的凹函数,所以对似然函数取极人值与对对数似然函数取极大值是等价的。3取了对数之后还可以跟信息熵等概念联系起来4关于凸函数有很多种说法,上凸函数和下凸函数,凸函数和凹函数等等,这里指的是二阶导数大」(等」)0的一类函数,而凹函数是其相反数为凸数的一类函数32期望最大化算法收敛性如何保证算法收敛呢?我们只用证明l(04+1)≥1(00)就可以了l(0(t11)∑∑(+1)1PX=x;2=2)(+(t+1∑∑nf(X=x;,z=z;)(+1)(t)o(tn /(r=i,Z=2(t)≥∑∑ahn(t)7(0其中第一个人于等于号是因为只有当a取值合适(琴生不等式等号成立条件)的时候才有等号成立,第二个人于等于号正是M步骤的操作所致。这样我们就知道l(θ)是随着迭代次数的增加越来越人的,收敛条件是值不再变化或者变化幅度很小。4应用举例4.1参数估计很直接的应用就是参数估计,上面举的例子就是参数估计42聚类但是如果估计的参数可以表明类别的话,比如某个参数表示某个样本是否属于某个集合。这样的话其实聚类问题也就可以归结为参数估计问题。References[]最大似然估计[oNline].Availablehttp://zh.wikipediaorg/wiki.%E6%9c%80%E5%A4%A7%E4%BC%BC%E7%84%B6%E4%BC%B0%E8%AE%A1[2] Ceppellini, r, Siniscalco, M.& Smith, C.A. Ann. Hum. Genet. 20, 97-115(1955)3 Hartley, H. Biometrics 14, 174-194(1958)4 Baum, L.E., Petric, T, Soulcs, G.& Weiss, N. Ann. Math. Stat 41, 164-171(1970)[ 5] Dempster, A P, Laird, N.M., Rubin, D B.(1977). "Maximum Likelihoodfrom Incomplete Data via the em algorithm. Journal of the royal statis-tical Society Series B(Methodological)39(1): 1-38. JSTOR 2984875 MR0501537[6]Whatistheexpectationmaximizationalgorithm[oNline].Avaiable:http//ai. stanford. edu/-chuongdo/papers/em tutorial pdf[7TheEmAlgorithmOnline.Availablehttp://www.cnblogs.com,jerrylead/ archive/2011/04/06/2006936html
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