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基于ABAQUS的高速切削切屑形成过程的有限元模拟
基于有限元分析软件ABAQUS的Johnson-Cook材料模型以及断裂准则模拟高速切削淬硬钢锯齿状切屑形态,并讨论刀具前角和锯齿状切屑形态对切削力的影响。研究表明仿真结果和试验结果是一致的,文中介绍的有限元模拟方法可以准确地模拟并预测高速切削淬硬钢时的切屑形成过程。刀4有限元模拟及试验结果将有限元模拟仿真预测的切屑形态与试验结果进行比较,如图2、图3、图4所示。预测的切屑形态结果以积分点处等效塑性应变( equivalent plastic strain,PEEQ)的形式显示。由图中可以看出,有限元预测的切屑形态与试验结果非常接近。图中PEEQ的最大值随刀具前角从-10°改变到10而逐渐减小,说明主剪切(a)锯齿状切屑显微照片(b)锯齿状切屑形态有限元模拟结果区内的切屑变形也随刀具前角的增大而减小。刀具前(a) A micrograph of(b) fe simulation result of serrated角对切屑形态有重要影响,当使用负前角时容易形成serrated chipchip morphology锯齿状切屑。图4锯齿状切屑形态有限元模拟仿真与试验结果的对比(Fig 4 Comparison between experimentally and numerically obtained80.70.6hI号0.5H总0.4(a)锯齿状切屑显微照片(b)锯齿状切屑形态有限元模拟结果(a)a micrograph of(b)fe simulation result of serrated肥0.2●试验结果 Experimental resulserrated chipch0:→摸拟结果 Simulation result图2锯齿状切屑形态有限元模拟仿真与试验结果的对比(yo=-10)1010Fig 2 Comparison between experimentally and numerically obtained刀具前角 Tool rake angle(°)chip morphology (Yo =-10)图5不同刀具前角条件下的锯齿化程度Fig 5 Sawtooth degree under different tool rake angles4000003600320.l6000012000(a)锯齿状切屑显微照片(b)锯齿状切屑形态有限元模拟结果4000(a)A microgram(b)FE simulation result of serrated0.000.050.100.150.20serrated chchip morphology时间Time×103/s图3锯齿状切屑形态有限元模拟仿真与图6锯齿状切屑形成时的切削力波动(y6=-10)试验结果的对比(y0=0)Fig 6 Efect of tool angle on the cutting force(%o =-10Fig 3 Comparison between experimentally and numerically obtained加而逐渐降低。刀具前角对切削力也有很大影响,如图6、图7和图8所示,平均切削力F的值随着刀具刀前通常使用锯齿化程度C9表示锯齿状切屑变形和角的增加而逐渐降低。切屑形态。Gs的定义如下Gs =(H-h,)/h(4)5结论Gs的测量方法如图2所示,Gs与刀具前角之间的关系本文的目的在于预测高速切削过程中的切屑形如图5图5说明模拟结果与试验结果符合很好,当切态。使用适合高速变形条件的 Johnson-Cook材料模削速度和进给量一定时,锯齿化程度随刀具前角的增型、断裂准则和 ABAQUS有限元软件,模拟并测量高速0.80LIU Zhan Qiang, WAN Yi, AI Xing. Cutting forces in High Speed Milling[J]. China Mechanical Engineering, 2003, 14(9): 734-737( In Chix0.60[2]Kishawy H A. An experimental evaluation of cutting temperature duringhigh speed machining of hardened D2 tool steel[ J]. Machining Science0.40and Technology, 2002, 6(1): 67-79[3]刘战强,艾兴.高速切削刀具磨损表面形态研究[门摩擦学学〓0.20报,2002,22(6):468-471RLIU Zhan Qiang, Al Xing. Wear characteristics of cutting tools in high尽0speed machining[J]. Tribology, 2002, 22(6): 468-471( In Chinese)0.000.050.100.150.20[4]赵文祥,龙震海,王西彬,等.高速切削超高强度钢时次表面层时间 Time x103/s的组织特性研究[J.航空材料学报,200,25(4):2025图7锯齿状切屑形成时的切削力波动(y0=0)ZHAO Wen Xiang, LONG ZhenHai, WANG XiBin, et al. Study on theFig7 Effect of tool angle on the cutting force(yo =00)metallurgical structure characters of sub-surface layer of ultra-high strength0.80alloy steel in high speed milling condition[J]. Joumal of Aeronautical MEterials, 2005, 25(4): 20-25( In Chinese)[5] Sung H R, Soo-Ik 0. Prediction of serrated chip formation in metal cutting0.60process with new flow stress model for AISI 1045 steellJ]. Joumal of Ma-terials Processing Technology, 2006,171: 417-4220.40[6】赵军,孟辉,王素玉,等.高速切削锯齿状切屑的有限元模拟[.工具技术,2005,39(1):29-310.20ZHAO Jun, MENG Hui, WANG SuYu, et al. Finite element simulatinganalysis of serrated chip formation in high speed cutting[J]. Tool Engi-0ing,2005,39(1):29-31( In Chinese)早0.000050.100.150.20时间 Time x103/s[7]Christian H, Svendsen B. Simmlation of chip formation during high-speed图8锯齿状切屑形成时的切削力波动(=10)cutting[ J]. Joumal of Materials Processing Technology, 2007, 186: 66Fig8 Effect of tool angle on the cutting force(%o = 100)[8] Klocke F, Raedt H W, Hoppe S. 2D-deform simulation of the orthogonal切削AISI4340钢过程中不同刀具前角条件下的切屑high speed cutting process[]. Machining Science and Technology, 2001形态和切削力,讨论刀具前角和切屑形态对切削力的5(3):323-340.影响。研究结果表明,模拟结果与试验结果能很好地9)]shkH,AbeE, Sahm a. Material aspects of chip formation in HSC相符。因此,本文使用的有限元模拟方法可以准确预machining[ J]. Amals of the CIRP- Manufacturing Technology, 2001, 50(1)测高速切削淬硬钢时切屑形成过程。参考文献( References)[1]刘战强,万熠,艾兴.高速铣削中切削力的研究[J.中国机械工程,2003,14(9):734-737.
- 2020-12-07下载
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LDA人脸识别matlab程序
【实例简介】Fisherface方法的实现是在PCA数据重构的基础上完成的，首先利用PCA将高维数据投影到低维特征脸子空间，然后再在这个低维特征脸子空间上用LDA特征提取方法得到Fisherface。
- 2021-11-13 00:33:11下载
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新英格兰10机39节点标准测试系统数据
电力系统IEEE39节点数据,含有暂态参数,希望对大家能有用
- 2020-12-05下载
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matlab图像融合工具箱
里面有很多常用的图像融合工具，具体的有小波变换、不同的小波基，变换的效果比对。
- 2020-12-05下载
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codesys库函数说明
codesys编程常用库函数说明包括模拟，标准库，pwm库等五个库
- 2020-12-05下载
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基于Matlab的线性系统分析与设计软件
【实例简介】线性系统通过微分方程来描述其运动特性。在系统中增加PID校正装置后，就能改变系统微分方程的系数，系统零、极点随之相应地变化，就能达到改善系统性能的目的。自动控制领域里有大量繁琐的计算与仿真曲线的绘制任务,用手工很难精确的画出系统的时间响应曲线。并且,对于较为复杂的系统, 因此,需要设计一套控制系统的教学软件,让学生可以直观、深刻地掌握控制系统的基础知识,准确、便捷地从仿真结果中进行推理,有效地补充和完善传统教学。本文主要研究PID算法原理以及其通过matlab软件完成其GUI操作界面，对算法原理进行仿真验证及比较。
- 2021-10-29 00:30:56下载
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iAQ-core C型传感器使用总结
在STM32F1平台上的iAQ-core C型传感器使用总结及其代码。是本人自创的，应该说是网络的首例。所以不要嫌弃资源分高，起码帮你节约一整个月的开发时间。
- 2020-12-06下载
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完整的数控刀具管理系统源程序
基于数据库的数控刀具管理系统的程序，数据库是Access，包含完整的代码，功能上包含数控刀具的入库、出库、借出、查询等功能。
- 2020-12-02下载
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APFC的matalab的仿真
【实例简介】
APFC的matalab的仿真，带反馈环
- 2021-10-14 00:31:15下载
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altera公司IP核使用手册.PDF
altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用A吉RAContentsChapter 1. About this MegaCore FunctionRelease informat1-1Device Family Support···Introduction.··········FeaturesOpen core plus evaluation1-3Performance···Chapter 2. Getting StartedDesign Flow衡·鲁·,看·,音番2-1Megacore Function walkthrough2-2Create a New quartus II Pi2-2Launch the mega Wizard Plug-in ManagerStep 1: Parameterize2-5Step 2: Set Up SimulationStep 3: Generate..,2-11Simulate the design2-13Compile the design2-13Pa Device2-14Set Up Licensing2-15ppend the license to yourdat file2-15Specify the License File in the Quartus II Software...2-15Example Simulation and Compilation..2-16Example quartus Ii project2-16Example simulation with Test Vectors,,,,,,2-16Chapter 3. SpecificationsyperTransport Technology Overview1HT SyStems3-2HT Flow ControlHyper Transport MegaCore Function SpecificationPhysical InterfaceSynchronization and alignment ...Protocol interfClocking Options.......HyperTransport Mega Core Function Parameters and HT Link Performance3-10Signals3-14CSR Module...3-31OpenCore plus time-Out BehaviorAppendix A. ParametersIntroduction鲁鲁鲁A-1Parameter listsDevice Family and Read Only registers···········,,,,,,,,,,A-1Base Address Registers番鲁,A-2Clocking OptionsA-3Advanced settingso March 2009 Altera corporationHyperTransport MegaCore Function User GuideAppendix B. Stratix Device Pin AssignmentsIntroductionB-1GuidelinesAppendix C. Example designGeneral descriptionAdditional informationRevision historyInto-lHow to Contact alteraInfo-1Typographic Conventions ..........Info-2Hyper Transport MegaCore Function User Guideo March 2009 Altera CorporationA吉RA1. About this MegaCore FunctionRelease InformationTable 1-1 provides information about this release of the Hyper Transport Mega CoretfunctioTable 1-1. Hyper Transport Mega Core Function Release InformationitenlDescription∨ ersion9.0Release dateMarch 2009Ordering codeIP-HTProduct ID(s)0098Vendor iD(s)6AF7Altera verifies that the current version of the quartus@ll software compiles theprevious version of each MegaCore function. Any exceptions to this verification arereported in the Mega Core lP Library release Notes and Errata. Altera does not verifycompilation with Mega Core function versions older than one releaseDevice Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families:Full support means the Mega Core function meets all functional and timingrequirements for the device family and may be used in production designsa Preliminary support means the Mega Core function meets all functionalrequirements, but may still be undergoing timing analysis for the device family;itmay be used in production designs with cautionTable 1-2 shows the level of support offered by the Hyper Transport MegaCorefunction for each of the altera device familiesTable 1-2. Device Family SupportDevice FamilySupportHard Copy Stratix@FullStratixFulStratix IIFulStratix‖GXPreliminaryStratix GXOther device familiesNo supportC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide1-2Chapter 1: About this MegaCore FunctionIntroductionIntroductionThe Hyper Transport Mega Core function implements high-speed packet transfersbetween physical(PhY) and link-layer devices, and is fully compliant with theHyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allowsdesigners to interface to a wide range of Hyper TransportTm technology(hT)enableddevices quickly and easily, including network processors, coprocessors, videochipsets, and ASICsFeaturesThe Hyper Transport Mega Core function has the following features8-bit fully integrated hT end-chain interfacePacket-based protocolDual unidirectional point-to-point linksUp to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction)200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devicesLow-swing differential signaling with 100-Q2 differential impedanceHardware verified with Hyper fransport interfaces on multiple industry standardprocessor and bridge devicesFully parameterized mega core function allows flexible, easy configurationFully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GXevice famillesApplication-side interface uses the Altera AtlanticTM interface standardManages Hr flow control, optimizing performance and ease of useIndependent buffering for each HT virtual channelAutomatic handling of ht ordering rulesStalling of one virtual channel does not delay other virtual channels(subject toorderingFlexible parameterized buffer sizes, allowing customization depending onsystem requirementsUser interface has independent interfaces for the HT virtual channels, allowingindependent user logic designCyclic redundancy code(crc) generation and checking to preserve data integrityIntegrated detection and response to common HT error conditions■ CRC errorsEnd-chain errorsFully integrated HT configuration space includes all required configuration spaceregisters and HT capabilities list registersHyper Transport MegaCore Function User Guideo March 2009 Altera CorporationChapter 1: About this MegaCore FunctionPerformance32-bit and 64-bit support across all base address registers bars)automatically handles all csr space accessesVerilog HDL and VHdL simulation supportOpen Core Plus EvaluationWith the Altera free Open Core Plus evaluation feature, you can perform the followingSimulate the behavior of a mcgafunction(Altera MegaCore function or AMPPmegafunction) within your systema Verify the functionality of your design, as well as quickly and easily evaluate itssize and speedGenerate time-limited device programming files for designs that includeMegaCore functionsProgram a device and verify your design in hardwareYou only need to purchase a license for the Mega Core function when you arecompletely satisfied with its functionality and performance and want to take yourdesign to productiono For more information about Open Core Plus hardware evaluation using theHyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"onpage 3-40 and AN 320: Open Core Plus Evaluation of megafunctionsPerformanceThe Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 showtypical performance and adaptive look-up table (alut) or logic element (LE)usagefor the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, andStratix GX devices respectively, using the Quartus@ II software version 7.1Table 1-3 shows the maximum supported data rates in megabits per second(Mbps)by device family and speed gradeTable 1-3. Maximum Supported Hyper Transport Data Rates (Note 1)Speed GradeDevice Family-36Stratix ll GX devices 1000 Mbps 1000 Mbps 800 MbpsNA(2)N/A(2NA(2)Stratix devices1000 Mbps 1000 Mbps 800 Mbps N/A(2)NA(2)NA(2)Stratix devicesN/A(2N/A(2)00 Mbps 800 Mbps 600 Mbps400 MbpsFlip-Chip packagesStratix devicesNA(2)NA(2)NA(2)600 Mbps400 Mbps400 Mbps(Wire Bond packagesStratix GX devicesN/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2)Notes to table 1-3(1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face(2) Devices ot this speed grade are not ottered in this device familyC March 2009 Altera CorporationHyperTransport Mega Core Function User GuideChapter 1: About this MegaCore FunctionPerformanceTable 1-4 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix II and Stratix II GX devicesTable 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX DevicesParametersMemoryUserRXCombinationalHT Link InterfacePosted Non-Posted Response ClockingALUTSLogicfMAX(MHz) MAx(MHz)Buffers BuffersBuffers Option(12)Registers M4K M512 ( 3)3)Shared3.5005200120500125(4RX/TX/Ref35005200500Ref/x8Shared36005400160500>150RX/TXShared4.0006,00016150RX/TX16Shared4,1006,200500125(4)RX/TX/RefShared4.1006200500125(4Ref/TxShared4.2006400160150RX/TXNotes to table 1-4.Refer to " Clocking Options "on page 3-7 for more information about these options(2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200(3)Figures for -3 speed grade devices only(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided byTable 1-5 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix and Stratix GX devicesTable 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX DevicesUser Interface fmaxParametersUtilizationHT Link fMAX MHz)MHZ)RXRXSpeed GradePosted Non-Posted Response Clocking Option LEsM4KBuffers BuffersBuffers)(2 Blocks.5-66Shared rx/tx/ref1240010073)100734448888Shared Ref/Tx 7, 60014400400100{3)100(3)Shared rxtx7,90016400400>125>100Shared rxtx8.900125>100168Shared Rx/T×Ref9,400124004001003)100316Shared ref/ ix9.500144001003)10073)16Shared rx/x9.700400125Notes to table 1-5:(1)Refer to Clocking Options"on page 3-7 for more information about these options(2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES(3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by fourHyper Transport MegaCore Function User GuideC March 2009 Altera CorporationA吉RA2. Getting StartedDesign FlowTo evaluate the HyperTransport Mega Core function using the Open Core Plus feature,include these steps in your design flowObtain and install the HyperTransport Mega Core functionThe HyperTransport Mega Core function is part of the MegaCore IP Library, which isdistributed with the Quartus ii software and downloadable from the altera websitewww.altera.como For system requirements and installation instructions, refer to Quartus II InstallationLicensing for Windows and Linux Workstations on the Altera website atwww.altera.com/literature/lit-qts.ispFigure 2-1 shows the directory structure after you install the HyperTransportMegaCore function, where is the installation directory. The default installationWindows is C: altera ; on Linux it islopt/alteraFigure 2-1. Directory StructureInstallation directorypContains the Altera MegaCore IP Library and third-party IP coresalteraContains the Altera MegaCore IP LibrarycommonContains shared componentshtContains the Hyper Transport Hyper Transport Megacore function files and documentationdocContains the documentation for the Hyper Transport MegaCore functionlibContains encrypted lower-level design filesexampleContains the design example for the Hyper Transport Mega Core function2. Create a custom variation of the Hyper Transport Mega Core function3. Implement the rest of your design using the design entry method of your choice4. Use the IP functional simulation model to verify the operation of your designo For more information about Ip functional simulation models, refer to the SimulatingAltera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook5. Use the Quartus II software to compile your designC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide2-2Chapter 2: Getting StartedMega Core Function WalkthroughIg You can also generate an Open Core Plus time-limited programming file,which you can use to verify the operation of your design in hardware6. Purchase a license for the hypertransport Mega Core functionAfter you have purchased a license for the Hyper transport mega Core functionfollow these additional steps1. Set up licensing2. Generate a programming file for the Altera device(s)on your board3. Program the Altera device(s)with the completed designMegaCore Function WalkthroughThis walkthrough explains how to create a custom variation using the AlteraHyper Transport IP Toolbench and the Quartus II software, and simulate the functionusing an ip functional simulation model and the modelsim software when you arefinished generating your custom variation of the function, you can incorporate it intoⅴ our overall projectIe IP Toolbench allows you to select only legal combinations of parameters, and warnsou of any invalid configurationsIn this walkthrough you follow these stepsCreate a New Quartus II Projecta Launch the MegaWizard Plug-in Manager■Step1: Parameterizea Step 2: Set Up Simulation■Step3: Generate■ Simulate the designTo generate a wrapper file and Ip functional simulation model using default values,omit the procedure described in"Step 1: Parameterizeon page 2-5Create a New Quartus ll ProjectCreate a new Quartus II project with the New Project Wizard, which specifies theworking directory for the project, assigns the project name, and designates the nameof the top-level design entityTo create a new project, perform the following steps1. On the Windows Start menu, select Programs> Altera> Quartus II tostart the Quartus lI software. Alternatively, you can use the Quartus II Web editionsoftware2. In the Quartus II window, on the File menu, click New Project Wizard. If you didnot turn it off previously, the New Project Wizard Introduction page appears3. On the New Project Wizard Introduction page, click NextHyper Transport MegaCore Function User Guideo March 2009 Altera Corporation
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