PCI Specification 3.0_PCI 3.0 规范
PCI 3.0 规范,英文原版。PCI Local Bus Specification Revision 3.0PCI LOCAL BUS SPECIFICATION, REV.3.0ContentsPREFACESPECIFICATION.……13INCORPORATION OF ENGINEERING CHANGE NOTICES (ECNS)1查音音鲁垂音音13DOCUMENT CONVENTIONS.………14l. INTRODUCTION…151.1. SPECIFICATION CONTENTS······151.2. MOTIVATION……151.3. PCI LOCAL BUS APPLICATIONS1. 4. PCI LOCAL BUS OVERVIEW171.5. PCI LOCAL BUS FEATURES AND BENEFITS……181. 6. ADMINISTRATION…………………202. SIGNAL DEFINITION m...mn.. 212.1 SIGNAL TYPE DEFINITION222.2. PIN FUNCTIONAL GROUPS..…………222.2.1. System Pins……,…,…,,…,…232.2.2. Address and data pins242.2.3. Interface Control Pins........................252.2.4. Arbitration Pins(Bus Masters Only)272.2.5. Error Reporting Pins....垂看d。普音看鲁D指音着音,。音音自。音音音。音自垂272.2.6. Interrupt Pins( Optional)……282.2.7. Additional signals312.2.8.64- Bit bus extension pins( Optiona)…,,……………………………332.2.9. TAG/Boundary scan Pins(Optional).......342. 10. System Management Bus Interface Pins(Optional)352. 3. SIDEBAND SIGNALS362. 4. CENTRAL RESOURCE FUNCTIONS.····:·····.·············363. BUS OPERATION373.1 BUS COMMANDS373.1. Command definition373. 1.2. Command Usage rules393.2. PCI PROTOCOL FUNDAMENTALS423.2.1. Basic Transfer Control····:············.················433.2.2. Addressing.............143.2.3. Byle lane and Byte enable usage……563.2.4. Bus Driving and Turnaround非音垂垂·非573.2.5. Transaction Ordering and posting….583. 2.6. Combining Merging, and Collapsing。。音垂。音62PCI LOCAL BUS SPECIFICATION, REV.3.03.3. BUS TRANSACTIONS……643.3.1. Read transaction……………653.3.2. Write transaction3.3.3. Transaction termination.………….673.4. ARBItRAtION音垂3.4.1. Arbitration Signaling protoco1..…………………893.4.2. Fast Back-to-Back Transactions. .........................................................93.4.3. Arbitration Parking………………………………………93.5 LATENCY953.5.1. Target Latency…….953.5.2. Master Data latency……….….…….,….….…..……..….,983.5.3. Memory Write Maximum Completion Time limit3.5.4. Arbitration Latency3.6. OTHER BUS OPERATIONS……·。垂,音着垂。着音D。。着。D音着音垂。音着D音非非音垂音非·非1103.6.1. Device selection…....…,103.6.2. Special cycle...........3.6.3. IDSEL Stepping…………,,…,…,,…,,…,,,,,………,…1133.6.4. Interrupt acknowledg3.7. ERROR FUNCTIONS春音·。音垂1153.7.. Parity ger1153.7.2. Parity Checking...........………,163.7.3. Address parity errors…...…,…163.7.4.Error Reporting…17173.7.5. Delayed Transactions and Data Parity Errors.......... 203.7.6. Error Recovery.............,213. 8. 64-BIT BUS EXTENSION1233.8.1. Determining bus Width during System initialization.…….…,1263.9.64- BIT ADDRESSING…..…………………………………………1273.10SPECIAL DESIGN CONSIDERATIONS.1304. ELECTRICAL SPECIFICATION.. m.m.9.1374.1. OVERVIEW…1374.1.1. Transition Road Map……1374.1.2. Dynamic vs Static Drive specificalion…1384.2. COMPONENT SPECIFICATION.……,………………,1…………………1394.2.1. 5V Signaling environment1404.2.2. 33V Signaling environment鲁鲁·垂垂1464.2.3. Timing specification1504.2.4.1determinate Inputs and metastable作,…………1554.2.5. Vendor provided specification..,..…,.…………….………17564.2.6. Pinout recommendation157PCI LOCAL BUS SPECIFICATION. REV.3.04.3. SYSTEM BOARD SPECIFICATION.………1584.3.1. Clock skew,…………………1584.3.2.R··1584.3.3. Pull-ups:····.················:·····…1614.3.4Power1634.3.5. System Timing Budget. ...........1644.3.6. Physical requirements............………674.3.7. Connector Pin assignments……/6844. ADD-IN CARD SPECIFICATION1714.4.1.Add- in Card Pin Assignment..,.,.,………………,1714.4.2. Power Requirements….,.,.,.,.,.,.,,.….,764.4.3. Physical requirements.........1785. MECHANICAL SPECIFICATION1815.1. OVERVIEW1812. ADD-IN CARD PHYSICAL DIMENSIONS AND TOLERANCES...........1825.3. CONNECTOR PHYSICAL DESCRIPTION…………………1954. CONNECTOR PHYSICAL REQUIREMENTS. ...............................2055. CONNECTOR PERFORMANCE SPECIFICATION……………,…2066. SYSTEM BOARD IMPLEMENTATION……………2076. CONFIGURATION SPACEb●看●鲁D鲁0e●2136. 1. CONFIGURATION SPACE ORGANIZATION音垂垂D·垂看垂…2136.2. CONFIGURATION SPACE FUNCTIONS .......................2166.2.1. Device ldentification鲁垂垂2166.2.2. Device Control鲁着鲁D垂2176.2.3. Device status2196. 2.4. Miscellaneous registers·······:········:···:·:··:·:······:··············4······:····2216.2.5. Base addresses……………………….22463. PCI EXPANSION ROMS2286.4. VITAL PRODUCT DATA.2296.5. DEVICE DRIVERS2296.6. SYSTEM RESET.…………………………2306.7. CAPABILITIES LIST2308. MESSAGE SIGNALED INTERRUPTS ...................................................................2316.8.1. MSI Capability Structure..............2326.8.2. MSl-X Capability and Table structures……………….……..2386.8.3. MSI and Msi-X Operation2467. 66 MHZ PCI SPECIFICATION2557. 1. INTRODUCTION2557.2. SCOPE7. 3. DEVICE IMPI TION CONSIDERATIONS7.3.1. Configuration space.......2557. 4. AGENT ARCHITECTURE256PCI LOCAL BUS SPECIFICATION, REV.3.07.5. PROTOCOL.……2567.5.1.66 MHZ ENABLE(M66EN) Pin definition.…………,………,,2567.52Latency..-..-.-2577.6. ELECTRICAL SPECIFICATION……………2577.6.. Overview·.·······.··2577.6.2. Transition roadmap to 66 MHz PCI··········.2577.6.3. Signaling Environment.......... 2587.6.4. Timing specification.……2597.6.5. Vendor provided specification. 26.57.6.6. Recommendations·.·························:············:······:········.:··········2657.7. SYSTEM BOARD SPECIFICATION.………,…,……………2667.7.1. Clock Uncertainty ......2667.7.2. Reset2677.7.3. Pullups..2677.7.4. Power..······.·.·::·····布鲁····音D鲁番。是。音垂看····非D∴2677.7.5. System Timing Budget7.7.6. Physical requirements2687.7.7. Connector Pin assi! nments…..,.,.,..,.,.,..,.,.,2697.8. ADD-IN CARD SPECIFICATIONS春音·。音垂2698. SYSTEM SUPPORT FOR SMBUSn2718. 1. SMBUS SYSTEM REQUIREMENTS2718.1.1. Power………278. 2. Physical and Logical sMBi27l8.1.3. Bus connectivit2728.1.4. Master and slave support....….….…..…..…..,2738.1.5. Addressing and Configuration2738.1.6.Ele2748.1.7. SMBus behavior on Pcl reset.........................2748.2.ADD- IN CARD SMBUS REQUIREMENTS…………2758.2.7Connection2758.2.2. Master and Slave Support...,.…..…….…,...….,2758.2.3. Addressing and Configuration……,…,…,……,…,…,…,….….…..….,2758. 2. 4. Power2758. 2.5. Electrical.········.····························275A. SPECIAL CYCLE MESSAGES●鲁●e鲁277A 1. MESSAGE ENCODINGS277A,2. USE OF SPECIFIC ENCODINGS ................................................277B. STATE MACHINES279B. 1. TARGET LOCK MACHINE·;.···.:..···:...···:··.·:····281B.2. MASTER SEQUENCER MACHINE283B 3. MASTER6PCI LOCAL BUS SPECIFICATION. REV.3.0C. OPERATING RULES289C 1. WHEN SIGNALS ARE STABLE..·····.:·.·.::···:·;289C.2. MASTER SIGNALS…音·。·看290C.3. TARGET SIGNALS…291C.4. DATA PHASES…292C.5. ARBITRATION.……………………………………292C.6. LATeNCY······:“·······293C.7. DEVICE SELECTION……………,……………………………293C 8. PARITY垂垂垂D·垂294D. CLASS CODESD 1. BASE CLASS OOH...w.w...296D 2. BASE CLASS OlH296D. 3. BASE CLASS O2H··297D 4. BASE CLASS O3H297D.5. BASE CLASS04H.………………………298D. 6. BASE CLASS OSH298D.7. BASE CLASS06H...………….…………………299D 8. BASE CLASS OZH,300D 9. BASE CLASS OSH.301D.10. BASE CLASS C9H.……………………………………………….301D.11. BASE CLASS OAH.…………………302D 12. BASE CLASS OBH302D. 13. BASE CLASS OCH303D.14. BASE CLASS ODH….…304D. 15. BASE CLASS OEH304D. 16. BASE CLASS OFH·····.····;····:·;:·······304D.17. BASE CLASS JOH.……………………………………………1305D, 18. BASE CLASS 11H305E. SYSTEM TRANSACTION ORDERINGE.I. PRODUCER- CONSUMER ORDERING MODEL308E. 2. SUMMARY OF PCI ORDERING REQUIREMENTS310E.3. ORDERING OF REQUESTS........................................311E.4. ORDERING OF DELAYED TRANSACTIONS…………312E.5. DELAYED TRANSACTIONS AND LOCK#.317E.6. ERROR CONDⅠ TIONS……318. EXCLUSIVE ACCESSES..m.msn0..319F.1. EXCLUSIVE ACCESSES ON PCIF 2. STARTING AN EXCLUSIVE ACCESS321F.3. CONTINUING AN EXCLUSIVE ACCESS323F 4. ACCESSING A LOCKED AGENT324F 5. COMPLETING AN EXCLUSIVE ACCESS325F. 6. COMPLETE BUS LOCK ......................................................................325IO SPACE ADDRESS DECODING FOR LEGACY DEVICES..9.... 327PCI LOCAL BUS SPECIFICATION, REV.3.0CAPABILITY IDS。,0329I. VITAL PRODUCT DATA331VPD FORMAT3I.2COMPATIBILITY……………………………334L.3. VPD DEFINITIONS3341.3.1. VPD Large and small resource Data Tags......·D垂看3341.3.2. VPD Example…3378PCI LOCAL BUS SPECIFICATION. REV.3.0FiquresFIGURE -I: PCI LOCAL BUS APPLICATIONS春DFIGURE 1-2: PCI SYSTEM BLOCK DIAGRAM17FIGURE2-1: PCI PIN LIST.…………..…………21figure 3-1: ADDRESS PHASE FORMATS OF CONFIGURATION TRANSACTIONS...... 48Figure 3-2: LAYOUT OF CONFIG ADDRESS REGISTER, ..............................................50Figure 3-3: HOST BRIDGE TRANSLATION FOR TYPE O CONFIGURATION TRANSACTIONSADDRESS PHASE51FIGURE3-4: CONFIGURATION READ…………156FIGURE3-5: BASIC READ OPERATION………………………65FIGURE 3-6: BASIC WRITE OPERATION66FIGure 3-7: MASTER INITIATED TERMINATION........................ 68FIGURE3-8: MASTER- ABORT TERMINATION…………69Figure 3-9: RETRY. ..........................................................................................................73FiGure 3-10: DISCONNECT WITH DATA. ........................74FiGure 3-11: MASTER COMPLETION TERMINATION:·:····:··.·4····.···…75FiGURE 3-12: DISCONNECT-1 WITHOUT DATA TERMINATION·····76Figure 3-13: DISCONNECT-2 WITHOUT DATA TERMINATION76FiGure 3-14: TARGET-ABORT…177figure 3-15: BASIC ARBITRATIONFIGuRE 3-16: ARBITRATION FOR BACK-TO-BACK ACCESS…94FiGurE 3-17: DEVSEL# AsSERTION·····:···.·:··110Figure 3-1 8: IDSEL STEPPING114FiGure 3-19: INTERRUPT ACKNOWLEDGE CYCLE. ...................................................114FIGURE3-20: PARITY OPERATION………116FIGuRE 3-21: 64-BIT READ REQUEST WITH 64-BIT TRANSFER125FIGURE 3-22: 64-BIT WRITE REQUEST WITH 32-BIT TRANSFER..........126FIGURE 3-23 64-BIT DUAL ADDRESS READ CYCLE129FIGURE 4-1: ADD-IN CARD CONNECTORS...........................138FIGURE4-2:V/ICURⅤ ES FOR5 V SIGNALING.…………………143FIGURE 4-3: MAXIMUM AC WAVEFORMS FOR 5V SiGnaling145FIGURE 4-4: V/I CURVES FOR 3.3V SIGNALING148FIGURE4-5:MAⅹ IMUM AC WAⅤ EFORMS FOR3.3ⅴ SIGNALING………150FIGURE 4-6: CLOCK WAVEFORMS151FIGURE 4-7: OUTPUT TIMING MEASUREMENT CONDITIONS.··4·:······.·154FIGURE4-8: INPUT TIMING MEASUREMENT CONDITIONS…………154FIGURE 4-9: SUGGESTED PINOUT FOR POFP PCI COMPONENT···“···:.···.····:·········157FIGURE4-10: CLOCK SKEW DIAGRAM………158FIGURE 4-1: RESET TIMING16lFIGURE4-12: MEASUREMENT OF TPROP,3.3 VOLT SIGNALING……………166FIGURE 5-1: PCI RAW ADD-IN CARD(3.3V, 32-BIT).183FIGURE 5-2: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 32-BIT)..........184FIGURE 5-3: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 64-BIT)....185FIGURE 5-4: PCI RAW LOW PROFILE ADD-IN CARD(3.3V, 32-BIT)..........186PCI LOCAL BUS SPECIFICATION, REV.3.0FIGURE5-5: PCI ADD-Ⅰ N CARD EDGE CONNECTOR BEⅤEL……187FIGURE56: PCI ADD-IN CARD ASSEMBLY(3.3V)……………………………88FIGURE 5-7: LOW PROFILE PCI ADD-IN CARD ASSEMBLY 3.3V)189FIGURE 5-8: PCI STANDARD BRACKET………190FIGuRE 5-9: PCI LOW PROFILE BRACKET191FIGURE 5-10: PCI STANDARD RETAINER···192FIGURE5-11: IO WINDOW HEIGHT∴………………193FIGURE 5-12: ADD-IN CARD INSTALLATION WITH LARGE IO CONNECTOR.......194FIGURE 5-13: 32-BIT CONNECTOR196FIGURE 5-14: 3.3V/32-BIT CONNECTOR LAYOUT RECOMMENDATION. ........................197FIGURE5-15:3.3V/64-BIT CONNECTOR198FIGURE 5-16: 3.3V/64-BIT CONNECTOR LAYOUT RECOMMENDATION 199FIGURE 5-17: 3.3V/32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES2(垂D·。垂,音着垂。着音D。。着。D音着音垂。音着音FIGURE 5-18: 3.3V/64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES….201FIGURE5-19: UNIVERSAL 32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES………………………………202FIGURE 5-20: UNIVERSAL 64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES203FIGURE5-21:PCⅠADD- IN CARD EDGE CONNECTOR CONTACTS……204FIGURE5-22: CONNECTOR CONTACT DETAIL………………205FIGURE 5-23: PCI CONNECTOR LOCATION ON SYSTEM BOARD208FIGURE5-24:32- BIT PCI RISER CONNECTOR……209FIGURE 5-25: 32-BIT/3.3V PCI RISER CONNECTOR FOOTPRINT210FIGURE 5-26: 64-BIT/3.3V PCI RISER CONNECTOR211FIGuRE5-27:64-BI/3.3ⅴ PCI RISER CONNECTOR FOOTPRINT∴………212FIGURE 6-1: TYPE OOH CONFIGURATION SPACE HEADER215FIGURE 6-2: COMMAND REGISTER LAYOUT217FIGURE6-3: STATUS REGISTER LAYOUT……………………………219FIGURE 6-4: BIST REGISTER LAYOUT222FIGURE 6-5: BASE ADDRESS REGISTER FOR MEMORY........... 225FIGURE 6-6: BASE ADDRESS REGISTER FOR L/O225鲁着D音看FIGURE 6-7: EXPANSION ROM BASE ADDRESS REGISTER LAYOUT.....,..... 228FIGURE6-8: EXAMPLE CAPABILITIES LIST…….231FIGURE6-9: MSI CAPABILITY STRUCTURES…..……233FIGURE 6-10: MSI-X CAPABILITY STRUCTURE238FIGurE 6-11: MSI-X TABLE STRUCTURE翻音。音239FIGurE 6-12: MSI-X PBA STRUCTURE…239FIGURE 7-1: 33 MHZ PCI VS 66 MHZ PCI TIMING······:··················257FIGURE7-2:3.3 V CLOCK WAVEFORM.…………259FIGURE 7-3: OUTPUT TIMING MEASUREMENT CONDITIONS263FIGURE -4: INPUT TIMING MEASUREMENT CONDITIONS263FIGURE75:TvAL(MAX) RISING EDGE…………264FIGURE 7-6: TVAL(MAX) FALLING EDGE·265FIGURE77:TVAL(MIN) AND SLEW RATE……26510
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车载智能计算平台白皮书（自动驾驶）
车载智能计算平台白皮书（自动驾驶）版权声明本白皮书版权属于中国软件评测中心,并受法律保护。转载、摘编或利用其它方式使用本白皮书文字或者观点的,应注明“来源:中国软件评测中心”。违反上述声明者,本单位将追究其相关法律责任目录、编制概要(一)编制背景二)编制目标三)编制方法四)特别声明车载智能计算平台内涵与范畴(一)自动驾驶技术目前存在三种发展路线二)汽车智能计算平台包括“车、云、网、库”三)车载智能计算平台是。级及以上自动驾驶的必要解决方案(四)车载智能计算平合的功能定位、车载智能计算平台关键技术发展现状(一)芯片由通用走向专用,类脑芯片提供全新架构二)车载智能计算平台操作系统功能需求不断细化成为主流软件架构三)车载以太网受到广泛关注和进入竞争关键期(四)实现实时动态高精度定位需多技术融合(五)安全需求不断拓展,预期功能安全备受关注(六)测试需求不断细化,车载智能计算平台测试标准尚未形成四、车载智能计算平台相关产业发展现状(一)国内外企业纷纷布局车载智能计算平台(二)互联网企业、整车厂与半导体企业积极布局芯片领域三)车控操作系统国外占据发展先机,开源操作系统或成最大赢家四)国内外汽车网络通信技术产业蓬勃发展(五)“集中众包”成为高精度地图制图新模式五、车载智能计算平台发展现状国内外对比)车载智能计算平台性能方面国外处于领先地位二)国外部分计算平台已实现量产、国内计算平台仍处于样机阶段三)忐片性能方面国内典型产品存在优势六、车载智能计算平台中长期发展趋势(一)自主式和网联式协同推进自动驾驶发展二)电子信息、通信技术与汽车多产业交叉愈加突显三)软硬件协同开发提高车载智能计算平合的综合效率(四)高度集成是未来车载智能计算平台的发展方向五)多种数据处理模式并存的现状仍将持续七、推动车载智能计算平台发展的措施建议(一)明确发展方向前瞻规划布局(二)建立专项基金培育创新能力(三)夯实产业基础完善产业结构四)对外开放交流加强国际合作附件:缩略语、编制概要(一)编制背景汽车工业是中国产业发展的重要驱动。中国汽车工业经过近年的发展,年汽车工业总产值占全国工业总产值的比重达到%,占全国的比重达%。中国汽车市场目前已是全球最大单体汽车市场,年产销量分别占世界汽车产销量的%和%,但千人汽车保有量仅为世界平均值的%,发展空间较大。随着汽车智能化、网联化、电动化和共享化的发展,汽车产业发展面临新一轮的变革机遇,我国应该加大投入,抓住机遇,加快推进汽车强国建设。智能网联汽车从交通运输工具日益转变为新型移动智能终端。汽车功能和属性的改变导致其电子电气架构随之改变,进而需要更强的计算、数据存储和通信能力作为基础,车载智能计算平台是满足上述要求的重要解决方案。作为汽车的“大脑”,车载智能计算平台是新型汽车电子电气架构的核心,也是新犁智能汽车电子产业竞争的主战场明确车载智能计算平合的定义和范畴、关键技术、产业现状以及发展路线,在此基础之上为车载智能计算平台关键技术进步和产业化应用推广提供措施建议,对推动我国智能网联汽车产业持续健康快速发展具有重要意义。《中国公路学报》编辑部口国汽车工稈学术研究综述中国公路学报(二)编制目标通过明确车载智能计算平台的内涵与范畴,界定汽车智能计算平台基本架构和车载智能计算平台功能定位。研究车载智能计算平台的技术框架,梳理车载智能计算平台的关键技术。探索车载智能计算平合相关产业组成,分析车载智能计算平合的产业链结构,研判产业发展趋势。旨在提出促进车载智能计算平台相关技术及产业发展的可行性措施建议,为行业主管部门提供决策参考,为行业健康有序发展提供指导依据(三)编制方法是研究学习国内外相关政策文献,充分借鉴参考国内外主要研究动态和成果。是调研国内外知名车载智能计算平台相关企业,汇集整理和分析来自实践应用的相关素材。三是邀请行业专家咨询评审。(四)特别声明研究范围聚焦技术和产业发展车载智能计算平台将涉及法律、道德、伦理、文化等诸多领域。本白皮书的编制主要是为了给相关行业主管部门和企业提供决策参考依据,集中在技术和产业两大层面展开研究,暂未涉及其他方面。研究内容仍有待进一步丰富完善本白皮书的主要观点和内容仅代表编制组目前对车载智能计算平台的研判和思考,欢迎各方专家学者和企业代表提出宝贵意见,共同推动白皮书的及时更新和纠偏。本白皮书为《车载智能计算平合白皮书(年)》,后续中国软件评测中心将会继续推出《汽车智能计算平台白皮书(系列)。二、车载智能计算平台内涵与范畴(一)自动驾驶技术目前存在三种发展路线年(国际汽车工程师协会)发布《标准道路机动车驾驶自动化系统分类和定义》,并于年月对标准进行了修订更新。标准将自动驾驶分为共个级别。人工驾驶(),即完全由驾驶员执行全部动态驾驶任务(),包括有主动安全系统介入的情况。辅助驾驶(),即由自动驾驶系统在连续的特定设计运行工况(下执行动态驾驶任务的横向或纵向车辆运动控制子任务(但不能同时),并由驾驶员负责完成动态驾驶任务的其余内容。部分自动驾驶(),即由自动驾驶系统在连续的特定设计运行工况下执行动态驾驶任务的横向和纵向车辆运动控制子任务,并由驾驶员负责完成驾驶环境监控,并对道路目标和状态做岀有效回应。条件自动驾驶(),即由自动驾驶系统在连续的特定设计运行工况下执行所有动态驾驶任务。但是要求驾驶员具备汽车功能保障意识,并随时可以对自动驾驶系统发布的干预请求,以及与动态驾驶任务相关的其他车辆系统的故障做出有效回应。高度自动驾驶(),即自动驾驶系统在连续的特定设计运行工况下执行全部动态驾驶任务和功能保障,不要求任何用户对干预请求做出回应。完全自动驾驶(),即由自动驾驶系统在任意连续的运行环境下,执行全部动态驾驶任务和功能保障,不要求任何用户对自动驾驶系统的干颈请求做出回应。
- 2020-12-04下载
- 积分：1
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