伪随机序列及其应用（肖国镇）
M序列 m序列 gold序列 详细原理内容筒介本书介细伪份阻机序列的理论与用a本书共分六章前三章介绍战性和非线性移位存器的基本理论。第四、五章讨论实紫应用中最为美心的伪随机序列的相关函数使性。幣六章介绍伪随机序列的各种陀用即在伪码测距、导航协码多址、激字数据加器、噪声产生器,数保密系统中的应用举例。本书雷用的数学卿识尽量用为工程术人员容晏接受的方式刚述。勤繈机序列的抡近几年来又发现了在一些新兴领城中用a多雄伪隘机胖列的研宽正在受到广泛的重祝。本书可作为通、骨达、导航、遥控、遘测及计算机等有关专业的大学生、折蜕生和工程技术人员的参考书伪视序判及其应肖「慎椠传甲王育身編着任;夺端一桌社出版新华书店北京发行所发行各地新华书店经售国工业出版社印刷厂印装850×1161/印张21/2330千字18年3月榘一版.1985年3月第一次印刷印数,0p001-4600统一书号:150834·2727足价n240元序伪随机序列(或称伪噪声序列)的理论与应用,从产生到发展,算来已有二十几年的历史了。但是,这项新理论与新技术并不象某些其它所谓新思掘那样,突然爆发出来,形成一阵热潮,尔后不久便还渐消声匿迹乃至无人问津了。伪随机序列的理论在它形成的初期,便在通信、雷达、导航以及密码学等重要的找术领城中获得了广泛的应用。而在近年来的发展中,它的应用范围远远超出了上述领域之外,如自动控制、计算机,声学和光学测量数字式跟踪和测距系额以及数字网络系统的故障检测等。正象它的丰富多采的应用吸引着许多工程技术工作者一样,它的优美奇妙的数学理论以及许多尚待解决的数学问题也引起了理论工作者的极大兴趣。为了进一步发展伪随机序列的理论与应用研究,我们认为在圃内出版一本既有一定理论深度又注重这一新理论广泛应用的书是适宜的。这正是我们试图写作这一本书的主要且的。在这方而,我们特别感谢万哲先教授的鼓励与支持,他曾多次建议我们编写一套有关伪随机码与编码裡论及其应用的书本书共分六章。前三章介绍线性利非线性移位寄存器的基本理论。这方面所需要的数学理论主要是伽罗瓦( Galois)域论。本书假定该者对这一理论已有一定程度的了解。对于不太熟悉这…理论的该者,可参看万哲先教授所著的《代数与辅码》这本理论著作。本书的第四、五两章讨论实际应用中最为关心的伪随机序列的相关函数特性。第六章介绍伪随机序列的各种应用。伪随机序列在工程技术上有很多成功的应用,由于涉及的面很广而又多样化,本书不可能包罗万象。但是,我们试图对伪随机序列的几种典型应用作一较为清晰的介绍。自然,难免在题材的选取上受到了主观医素的影响。好在书末列入了有关的参考文献,以供读者去深入研究更广泛的裸题。研究生何大可同志在本书的写作过程中帮了很大的忙。他在本书的某些部分做了整理加工以及抄写、绘图的工作,并为木书中所介绍的一些算法编制了计算程序。考到多元伪随桃序列的理论与应用的新近发展,已将此项内容作为附录列入本书。书末有关的附表以及这一附录都是何大可同志编写的。作者还感谢西北电讯工程学院资料室的同志在本书写作过程中所给予的支持和帮助。感谢编码讨论斑同志们的戟励、批评和建议。出于我们的水平有限,本书难免会有许多缺点及不当之处,诚悬地新望得到广大读者批评和指正目录笫一章反馈移位寄存器的基本概念……………■b■■日■●■tD萨多1.1反馈私位寄存器h■日中冒暑白日日h山山日斷■中■晋ψ斷4晋冒b■日甲【看■■中卢卩■「日■卩■↓昌51.2反馈逻辑函数…;……………*…………………………71.3线性反馈移位寄存器及非线性反馈移位寄存器ta4++131.4有向图的一些基本概念…1.5迪布瑞菌古德( de brts-Good)图…“………………"1.6周期性与閣……………………………………………………s1.7两个简单移位寄存器的分析"“引F§18布尔函数与某一变元无关的判定准则………………"53笫二章线性反做移位寄存器序列……………"…………s9§2.1线性馈移位寄存器序列………………………………592.2纔性移位窬存器序列的周性23非退化线性移位窬存器状态图中圈长的丹布与圈的个数………652.4m序列……………“………78§2,5m序列的伪随机性…·d■■1·■■·■dp2.6线性递归方程的解法白日即自司■口··bb■如b画即■44b即4■■甲bbd92.7线性移位寄存器序列的果样9g2.8线性移位寄存器的综合…………………"………………l0g第三章非线性反馈移位寄存器序列…23§3.1非线性移位寄存器分析申『P■申卓血p2388.2M序列853.3非线性移位寄存器的综合iSi笫四章序列的相关函数卓卓章·d754.1序列相关函数的一般性质……………"………l474.2m序列的互祁关函数■噜『噌■■·■血曾■鲁■曾音會血會■自曾P口■口■『■口4■自…F34.3好的序列旋一戈尔德(God)序列族…"………l84.4其它好的序列族345非周期自相关函小的序列……………!出FA.6互补序列自P■_p即音■冒4幽p■44個音■_4P甲P■■■产§4.7多相序列h4山山20§4.8二元正交序列族…………………………………"………21第五章复合序列及其p相失函数2205.1序列的组合及其舆福关性…22085.2序列的布尔组合及其相关函数…b『『…………235.3模二和复码及其相关函数…………………………285.4复码自相关函嶽的解析计算法…2335.5复合序列的功率谱度……-……M"?37第六章伪随机序列的应用29紧6.1伪码测距原理…a▲249§B.2导航中的应用…【司『■■P■■血■…‘2f§63份码多址系统……………………………"…""2776.4数字嶽据加乱器28了865随机序列作为噪声产生器■上■■■■血“『■『■6,6数据傑密系统中的应用…………………………30l附录多维伪随机阵列…307邹71基本概念…………………"……""""………""…""37§7.2具最大商积基块周期乎面的综合…………甲3f4邹7.3具最大容积基块的多维聞期阵列及其综合卜山卩■■昏■■■■Lp■q↓警7,4周期平面的其它踪合法………"了5?.5周期平面的应用…………………………………"364附表一F2上不可约多项式的表(次数≤10)附表二F2上不可约三项式x十x十1的表〔2≤n≤100,1≤≤!2)374附表三F2上本原多项式的表(次数≤168,每个次数一个)附表四GF(q)上本原多项式的表(g=3,4,8,次数≤10)8附表五产生5级(二元)M序列的移位寄存器的反馈函数∫(x:x2,…,)的表(2048个)380参考文390第一章反馈移位寄存器的基本概念大家知道,一般控制系统大体上可分为动态系统与静态系统两大类。在所谓动态系统中,其系统特性是由含有时间参数的输出、输入变嚣的微分方程来描述。而在静态系统中,其系统特性可用没有时间参数的方程来描述。此时,系统在每一瞬间的输出仅由同一瞬间的辖入来决定。近年来在数宇设备中所考虑的,是种特殊的静态系统,即所谓二元系统。这种系统中的变量只取两个值,简单地表示为“0”和“1”。描述这种二元系统的方程可出含有逻辑运算“与”、“或”、“非”的关系来表示。有时也把这种二元系统称作静态辑系统,它是电子工程实践中最为重要的静态系统。在本书中我们所要讨论的是一种典型的二元系统,即所谓反馈移位寄存器。由于这种装置在无线电电子技术中具有广泛的应用,因而近年来特别引超人们的重视。在本章中,我们将对反馈位寄存器的基本结构及其有关概念做一大致的介绍。从本质上说,我们的论述可以在q元域GF(q)上进行。但是,考虑到目前具有实用价值的仍然是二元的情况,因此我们仅在二元城GF(2)中进行讨论。为简便,今后用F与E2分别代装GF(q)号GF(2)§1.1反馈移位寄存器现在我们来考察一般反馈移位寄存器的基本结构。图1.1.1是这种反馈移位寄存器的框图。它由串联的个二元移存器及个开关网络构成众所周知,每一个二元存储器即为一个双稳态触发器,它的两钟状态分别记为“1”与“0”,每个触发器看作级。因此,图⊥.1,1可以看作是一个r级反馈彬位衔存器。图时钟脉冲汗头网新图1.1.一般反移位寄存器示意图中上面一排小方框,自左至右,分别称为第1级、第2级、第8级、…第r-1级及第r级存储器。下面一个长方框内所示的开关网络可视为具有r个输入端及一个输出端的组合门电路。从理论上来说,这“組合门电路可由一个含有r个逻辑变元x1,x2…,x的布尔( Boole)数∫(x,x:,来标志。我们称这一函数为该组合门电路的反馈逻辑函数。上述反馈移位寄器的工作是受时钟脉冲控制的。假定在第j个时钟移位脉冲(第j拍)到来时,移位寄存器的状态是j于是,再来一个时钟脉冲使j增至j十1时(第j+1拍),最右面的一级在第j拍之状态a即为输出,并且每个存贮器在第∫+1拍之状态恰为邻接于它的左面的存贮器在第拍之状态。同时,这r个寄存器在第j拍之状态输入至开关网络后,相应的输出为a=f(a,an+…,aa-),它反馈给最左面一级,作为第1级寄存器在第∫十1拍的状态。这样来,从状态转移的角度来看,从第氵拍过渡到第j十1拍后,就使移位寄存器的状态由(apa…,a}-四1)变换到(qa;),记作Tr(a吁…,ax1)→(吁,*…,1!a1),或T af-ss a-r)=(a1+,a↓2费称T为这一反馈移位寄存器的状态转移变换。从上面的分析不难看出,对于反馈移位寄存器来恍,超决定性作用的是那个组合门电路的反馈逻辑酹数f〔x1,x…,x)它是由r个逻辑变元x1x通过“与”、“或”、“非”等逻辑运算联接起来的关系式。下面,我们通过两个具体例子来说明反馈移位寄存器的功能例1.1.1考虑如图1.1.2所示之三级反馈移位寄春器。这个图112三级反债移位寄存器示意图反馈移位寄存器的工作揹况是:当第j拍处于状态(a;sq1)时,第氵+1拍便处于状态(a=2,其中a=a,3这里的符号“+”是指模2如法。显然,这个反馈移位寄存器的组合门电路就是简单的模2如法器。它所对应献反馈逻辑函数是∫(%1,x3xs)=x1x该反馈移位寄存器的状恣转移情况如下表所示。
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MIPI Alliance Specification for D-PHY
MIPI Alliance Specification for D-PHY Version 1.00.00 – 14 May 2009配合“MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2)“ 一起看。http://download.csdn.net/detail/micro_st/4242724Version1.00.0014-May-2009MIPI Alliance Specification for D-PHY2 The material contained herein is not a license, either expressly or impliedly, to any IPR owned or3 controlled by any of the authors or developers of this material or MIPl. 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LOSS OF DATA OR ANY INCIDENTAL.21 CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER22 CONTRACT TORT WARRANTY OR OTHERWISE ARISING IN ANY WAY OUT OF THIS OR23 ANY OTHER AGREEMENT SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL24 WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH25 DAMAGES26 Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is27 further notified that MIPI: (a)does not evaluate, test or verify the accuracy, soundness or credibility of the28 contents of this Document;(b)does not monitor or enforce compliance with the contents of this Document29 and (c)does not certify, test, or in any manner investigate products or services or any claims of compliance30 with the contents of this Document. The use or implementation of the contents of this Document may31 involve or require the use of intellectual property rights ("IPR")including(but not limited to) patents32 patent applications, or copyrights owned by one or more parties, whether or not Members of MIPIMIPI33 does not make any search or investigation for IPR, nor does miPi require or request the disclosure of any34 IPR or claims of IPR as respects the contents of this document or otherwise35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed36 MIPI Alliance. Inc37 c/o IEEE-ISTO38 445 Hoes lane39 Piscataway, NJ0885440 Alin: Board SecretaryCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY42 Contents43 Draft Version 1.00.00-14 May 2009441 Overview1451.2 Purpose.…..,.,.,,.,..472 Terminology…2.1 Definitions162.2 Abbreviations…172.3 Acronyms51 3 D-PHY Introduction523.1 Summary of Phy functionality533.2 Mandatory Functionality················2054 4 Architecture21554.1 Lane modules…564.2 Master and slave2254.3 High Frequency Clock Generation22584.4 Clock lane data lanes and the phy-Protocol interface.224.5 Selectable Lane Options·;····················234.6 Lane Module Types4.6.1 Unidirectional Data Lane…264.6.2 Bi-directional data lanes26634.6.3 Clock lane.274.7 Configurations….7654.7.1 Unidirectional Configurations............664.7.2Bi-Dal Half-Duplex Configurations674.7.3 Mixed Data Lane configurations32Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidential111Ⅴ ersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY695.1Transmission Data Structure,………………………∴335.1.1Data unitsa勹5.1.2 Bit order Serialization and De-Serialization33725.1.3 Encoding and decoding735.1.4 Data Buffering,33745.2 Lane States and Line levels755.3 Operating Modes: Control, High-Speed, and Escape5. 4 High-Speed Data Transmission··········;·5. 41 Burst payload data785.4.2 Start-of-Transmission795.4.3End-of-transmission805.4.4 HS Data Transmission burst.365.5 Bi-directional data Lane turnaround5.6 Escape Mode41835.6.1Remote triggers42845.6.2 Low-Power data Transmission43855.6.3 Ultra-Low Power State865.6.4 Escape Mode State Machine43875.7 High-Speed Clock Transmission885. 8 Clock lane Ultra-Low Power State50959 Global Operation Timing Parameters.……5.10 System Power States56915.11 Initialization56925.12 Calibration5.13 Global Operation Flow Diagram57945.14 Data Rate Dependent Parameters(informative)955. 14.1 Parameters Containing Only UI values965. 14.2 Parameters Containing Time and Ul values59Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY5.14.3 Parameters Containing Only Time Values…………5.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent6 Fault detection611006.1 Contention detection1016.2 Sequence Error Detection.……611026.2.1 SoT Error621036.2.2 SOT Sync Error1046.2.3 EoT Sync Error1056.2. 4 Escape Mode Entry Command error.1066.2.5 LP Transmission Sync error621076.2.6 False Control error1086.3 Protocol Watchdog Timers(informative)62l096.3.1 HS RX Timeout6.3.2HS TX Timeout………………·················+···:··:·················∴62l116.3.3Escape mode timeout62l126.3. 4 Escape Mode Silence Timeout6.3.5 Turnaround errors114 7 Interconnect and Lane Configuration.641157.1 Lane configuration1167.2 Boundary Conditions.....…647.3 Definitions………64l187.4S- parameter Specifications………….651197.5 Characterization Conditions207.6 nterconnect Specifications………1217.6.1 Differential characteristics1227. 6.2 Common-mode characteristics671237.6.3 Intra-Lane Cross-Coupling1247. 6. 4 Mode-Conversion limitsCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY1257.6.5 Inter-Lane Cross-Coupling671267. 6.6 Inter-Lane static skew1277.7 Driver and receiver Characteristics1287.7.1 Differential Characteristics1297. 7.2 Common-Mode characteristics1307.7.3 Mode-Conversion Limits1317.7.4 Inter-Lane Matching132 8 Electrical Characterislics701338.1 Driver characteristics1348.1.1 High-Speed Transmitter1358.1.2 Low-Power Transmitter1368.2 Receiver Characteristic·…············…·······…8301378.2.1 High-Speed Receiver801388.2.2Low- Power receiver.................….….821398.3 Line contention detection1408.4 Input Characteristics8441 9 High-Speed Data-Clock Timing1429.1 High-Speed Clock Timing861439.2 Forward High-Speed Data Transmission Timing871449.2.1 Data-Clock Timing Specifications1459.3 Reverse High-Speed Data Transmission Timing89146 10 Regulatory Requirements91147 Annex A Logical PHY-Protocol Inter face Description(informative)92148A 1 Signal Description149A 2 High-Speed Transmit from the Master Side150A3 High-Speed receive at the slave Sidel00151A 4 High-Speed Transmit from the Slave side152A.5 High-Speed Receive at the Master SideIOICopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY153A6 Low-Power Data Transmission102154A7 Low-Power Data Reception.103155A 8 Turn-around156 Annex B Interconnect Design Guidelines (informative)105157B. 1 Practical distances105158B 2 RF Frequency Bands: Interference.105B3 Transmission Line design160B4 Reference Layer.106161B 5 Printed-Circuit board106162B6 Flex-foils106163B 7 Series resistance106164B 8 Connectors106165 Annex C 8b9b Line Coding for D-PHY(normative)107166C 1 Line Coding Features...·············108167C.1.1Enabled Features for the Protocol108l68C 1. 2 Enabled Features for the Phy108169C2 Coding scheme170C 2.1 8b9b Coding Properties.....108171C 2.2 Data Codes: Basic Code Set……….109C.2.3 Comma Codes: Unique Exception Codes110173C 2.4 Control Codes: Regular Exception Codes…10174C.2.5 Complete Coding Scheme………175C 3 Operation with the D-PhY…11117yload: Data and Control177C.3.2 Details for Hs transmission………112178C.3.3 Details for LP Transmissionl12179C 4 Error Signal180C5 Extended PplCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialⅤ ersion1.00.0014-May-2009MIPI Alliance Specification for D-PHYl81C.6 Complete Code Set.….….l15182Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidentialv111Version1.00.0014-May-2009MIPI Alliance Specification for D-PHYl83Figures184 Figure 1 Universal Lane Module functions21185 Figure2 Two Data Lane PHY Configuration.…………23186 Figure 3 Option Selection Flow Graph4187 Figure 4 Universal Lane Module Architecture25188 Figure 5 Lane Symbol Macros and Symbols Legend189 Figure 6 All Possible Data Lane Types and a basic Unidirectional Clock lane190 Figure 7 Unidirectional Single Data Lane Configuration30191 Figure 8 Unidirectional Multiple Data Lane Configuration without LPDT∴.30192 Figure 9 Two Directions Using Two Independent Unidirectional PHYs without LPDT.........31193 Figure 10 Bidirectional Single Data Lane Configuration31194 Figure 1l Bi-directional Multiple Data Lane Configuration......32195 Figure 12 Mixed Type multiple data Lane Configuration32196 Figure 13 Line level34197 Figure 14 High-Speed Data Transmission in Bursts36198 Figure 15 TX and rX State Machines for High-Speed Data Transmission37Figure16 Turnaround Procedure.……39200 Figure 17 Turnaround State Machine40201 Figure 18 Trigger-Reset Command in Escape Mode202 Figure 19 Two Data Byte Low-Power Data Transmission Example203 Figure 20 Escape Mode State Machine204 Figure2 I Switching the Clock Lane between Clock Transmission and low- Power mode………….47205 Figure 22 High-Speed Clock Transmission State Machine49206 Figure 23 Clock Lane Ultra-Low Power State State Machine········+·+···+·4···207 Figure 24 Data Lane Module State Diagram57208 Figure 25 Clock Lane Module state diagram58209 Figure 26 Point-to-point InterconnectCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidential
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