登录
首页 » VHDL » JOP字节码获取的源码,很重要,具体FPGA中实现

JOP字节码获取的源码,很重要,具体FPGA中实现

于 2022-01-26 发布 文件大小:2.61 kB
0 141
下载积分: 2 下载次数: 1

代码说明:

JOP字节码获取的源码,很重要,具体FPGA中实现-JOP byte code access to the source code is important to achieve specific FPGA

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • verilog111.rar
    verilog 的东西好好用的呢,那是verilog 学习者的必备东西哦(verilog things properly used it, it is an essential learners verilog things oh)
    2007-05-20 10:23:46下载
    积分:1
  • STM32F407FFT
    说明:  使用STM32官方提供的DSP库进行FFT,虽然在使用上有些不灵活(因为它是基4的FFT,所以FFT的点数必须是4^n),但其执行效率确实非常高效,看图1所示的FFT运算效率测试数据便可见一斑。该数据来自STM32 DSP库使用文档(. Using the official DSP library provided by STM32 for FFT is not flexible in use (because it is the FFT of base 4, so the number of FFT points must be 4 ^ n), but its execution efficiency is really very efficient, as can be seen from the test data of FFT operation efficiency shown in Figure 1. This data comes from STM32 DSP library usage document)
    2020-06-20 19:00:02下载
    积分:1
  • fenpinqi de vhdlchengxu gongnengfnagzhen,政
    分频器的VHDL程序,完整的建立工程,编译,功能功能仿真,验证-fenpinqi de vhdlchengxu gongnengfnagzhen,yanzheng
    2022-02-21 21:03:34下载
    积分:1
  • verilog-ethernet
    说明:  Collection of Ethernet-related components for gigabit, 10G, and 25G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and a 10G/25G combination MAC/PCS/PMA module. Includes various PTP related components for implementing systems that require precise time synchronization. Also includes full MyHDL testbench with intelligent bus cosimulation endpoints.
    2021-04-17 23:38:52下载
    积分:1
  • DDS
    可以实现DDS 的正负线性扫频以及在线参数设置(DDS ad9914/ad9915 code)
    2020-09-07 15:28:03下载
    积分:1
  • DDR_SDRAM_verilog
    说明:  DDR(双速率)SDRAM控制器参考设计verilog代码,可以直接用的,很好的(DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good)
    2021-03-13 16:39:24下载
    积分:1
  • these files are written in verilog but i am uploading in text format
    these files are written in verilog but i am uploading in text format
    2023-08-21 20:45:02下载
    积分:1
  • wide_cbf
    宽带波束形成,设计FIR滤波器系数。带宽为500Hz--700Hz,采样率为3000Hz,对白噪声序列进行滤波,即得到有限带宽的宽带时域信号(Broadband beamforming design FIR filter coefficients. Bandwidth of 500Hz- 700Hz, sampling rate of 3000Hz, filtered white noise sequence, ie limited bandwidth broadband time domain signal)
    2013-03-19 09:40:45下载
    积分:1
  • 基于FPGA的键盘程序代码,可用单片机控制
    基于FPGA的键盘程序代码,可用单片机控制-FPGA-based keyboard program code can be used SCM control
    2023-04-22 05:40:04下载
    积分:1
  • ex11
    说明:  该模块实现了FPGA的uart串口收发功能(The module realizes UART serial port transceiver function of FPGA)
    2020-09-09 11:58:09下载
    积分:1
  • 696518资源总数
  • 106164会员总数
  • 18今日下载