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gobang
一个用verilog实现的五子棋程序,用在fpga上,连接显示器,可选择与电脑对战或是双人对战,按wsad控制方向,回车控制落子,程序会自动判断输赢并显示结果(A 331 procedures implemented by verilog, used in fpga, connect the monitor, you can choose to play against the computer or a double play, press wsad control the direction, carriage control Lazi, the program will automatically determine the winners and losers and display the results)
- 2015-03-30 13:13:35下载
- 积分:1
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8-fft
FFT 8 PT RDX 2 USING VERILOG
- 2014-03-31 02:35:31下载
- 积分:1
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18_vga_test
基于Xilinx Spartan6系列的fpga的VGA实现(Based on Xilinx Spartan6 series fpga VGA implementation)
- 2019-04-01 13:47:46下载
- 积分:1
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UART
UART文件 包括发送器 接收器 fifo 测试文件(UART file includes a receiver transmitter fifo test files)
- 2016-06-06 20:35:02下载
- 积分:1
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示波器设计源工程
说明: 示波器设计,首先,AD模块对模拟信号进行采样,触发电路根据采样信号判断触发条件。满足触发条件后,连续采样一定数量的点(本系统中为640个点),存储到RAM中。峰峰值、频率计算模块对RAM中储存的波形数据进行计算,得到波形的频率以及峰峰值;VGA模块将波形显示出来,并显示计算得到的峰峰值和频率数值。(Firstly, the ad module samples the analog signal, and the trigger circuit judges the trigger condition according to the sampling signal. After meeting the trigger conditions, a certain number of points (640 points in this system) are sampled continuously and stored in RAM. The peak to peak and frequency calculation module calculates the waveform data stored in RAM to obtain the frequency and peak to peak of the waveform; the VGA module displays the waveform and displays the calculated peak to peak and frequency values.)
- 2021-01-02 17:29:54下载
- 积分:1
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AMBA总线的Verilog语言模型
AMBA总线的Verilog语言模型
包括:AHB总线仲裁器,AHB-APB总线桥接器,AHB总线上从设备ROM模型,AHB总线上从设备RAM模型,参数定义。
- 2022-03-17 12:48:41下载
- 积分:1
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在quartus下搭建的数字锁相环
在quartus下搭建的数字锁相环,能实现频率自动跟踪。(The digital phase-locked loop built under quartus can realize automatic frequency tracking.)
- 2020-06-21 01:00:02下载
- 积分:1
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ovl_arm 开源arm
没什么可说的,SOC中经常用到,希望可以方便到大家。没什么可说的,SOC中经常用到,希望可以方便到大家。没什么可说的,SOC中经常用到,希望可以方便到大家。没什么可说的,SOC中经常用到,希望可以方便到大家。
- 2022-03-07 02:32:53下载
- 积分:1
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ODriveFPGA-master
使用FPGA控制永磁同步电机的代码,实现对永磁同步电机的控制功能。(Motor control by using FPGA)
- 2020-10-29 09:19:58下载
- 积分:1
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gcounter1
数字钟vhdl实现,在线测试无误,具有闹钟,对表功能(Digital clock vhdl implementation, online testing is correct, with alarm, the table function)
- 2013-10-19 22:06:16下载
- 积分:1