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verilogCRC32
32位bit输入的CRC32校验，verilog的代码，以及modelsim的testbench代码(The encode of CRC32 with 32bit-inputs based on verilog, and according encode of testbench)
- 2012-03-07 10:22:58下载
- 积分：1
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DE2_LCM_DISP_sucess
这是altera公司的DE2-35开发板下的一个液晶显示屏源程序代码工程，液晶显示屏是友晶公司的，包括液晶显示屏的驱动以及显示等模块有需要的人，可以下载
(Altera DE2-35 development board of the company, a liquid crystal display source code engineering, LCD display the Terasic, including LCD driver module and display needs, you can download)
- 2012-10-19 21:04:47下载
- 积分：1
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busok
高频卡读写原理及技术编程应用--卡的读取，写入。(High-frequency card reader technology)
- 2011-07-19 11:16:22下载
- 积分：1
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用VHDL语言编写的代码，以供大家学习和交流，方便大家学习！...
用VHDL语言编写的代码，以供大家学习和交流，方便大家学习！-prepared using VHDL code for all to study and exchange to facilitate learning!
- 2022-02-04 03:08:53下载
- 积分：1
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prj_ex_5
自动化仿真平台的搭建使用代码，经过具体的仿真和优化，发现代码完全可用(The automated simulation platform is built using code, and after specific simulation and optimization, it is found that the code is fully available)
- 2017-09-21 15:11:33下载
- 积分：1
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Based on quartus a 3
基于quartus的3-8译码器,可作为大型系统的译码器模块-Based on quartus a 3-8 decoder can be used as large-scale system decoder module
- 2022-03-14 15:00:50下载
- 积分：1
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USB_xilinx_vhdl
Giao tiep Univesan ...
- 2020-06-20 03:00:02下载
- 积分：1
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IIR
使用verilog语言描述的二阶巴特沃斯IIR滤波器，程序中有参数说明，已经运行通过(Using verilog language to describe the second-order Butterworth IIR filter, the program has parameter description has been run through)
- 2013-06-18 16:30:35下载
- 积分：1
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Xilinx-Timing
Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)
- 2013-05-17 09:31:26下载
- 积分：1
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f_adder
该工程描述的是一位全加器，可以用此作为基础，搭建多位全加器(The project description is a full adder can use this as a basis to build a number of full adder)
- 2013-04-21 10:30:16下载
- 积分：1
