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MIPS_LANG
说明： verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)
- 2020-06-18 04:40:02下载
- 积分：1
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FPGA 视频录制
OV7725 相机使用 I2C 通信接口。将数据保存到 SDRAM，并呈现到 VGA 显示。它可以支持所有可用的显示分辨率。
- 2022-03-25 04:13:36下载
- 积分：1
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8bit_frequency_meter
说明： 设计一个8位的简易频率计，测出信号的频率，即1s内变化的次数。(An 8-bit simple frequency meter is designed to measure the frequency of the signal, i.e. the number of changes in one second.)
- 2020-06-21 13:40:01下载
- 积分：1
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傅里叶变化
快速付里叶变换子程序所需 RAM 空间以输入的首地址为基址,向增加的方向扩展(Fast Fourier Transform subroutine RAM space required to input the first address of the site was to increase the direction of expansion)
- 2005-08-03 16:04:51下载
- 积分：1
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or1200.tar
OpenRISC 1200 cpu with integrated patches to support ORPSOC and FuseSOC builders
- 2014-12-20 04:40:23下载
- 积分：1
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VGA_Controller
用以VGA显示的小程序，很实用，挺有价值的(VGA display for a small program, very practical, quite valuable)
- 2013-07-24 08:58:24下载
- 积分：1
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FIR_poroje
this project is about FIR FIlter By VHdl codes in the ISE.
- 2013-09-29 19:25:16下载
- 积分：1
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FIRVerilogHDL
it is a fir filter program VerilogHDL.(it is a filter program VerilogHDL fir.)
- 2007-04-12 22:21:26下载
- 积分：1
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zhuangtaiji
这是一个最最常用的用vhdl写的状态机，几乎哪儿都用得到(a very good state machine)
- 2009-03-14 19:25:29下载
- 积分：1
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exercise3
用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分：1
