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异步FIFO的设计仿真和综合技术
Simulation and Synthesis Techniques for Asynchronous FIFO Design
- 2022-07-12 03:34:39下载
- 积分：1
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Idddc_30mF
中频70M，30M带宽LFM信号，采样率为102.4M，，数字下变频后，还进行了三倍抽取，最后还得到I，Q两路信号
(IF 70M, 30M bandwidth LFM signal, the sampling rate 102.4M, under digital variable frequency after also carried out three times extracted, and finally also received the I and Q signals)
- 2012-07-25 23:56:30下载
- 积分：1
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It s a 8051 VHDL source code issued by Original.
它是一个8051 VHDL源代码发布的原创。
- 2022-06-17 06:19:21下载
- 积分：1
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基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。...
基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。-something about turbo。
- 2023-02-09 02:35:04下载
- 积分：1
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tPad_Camera
tPad DE2-115/70开发板可用的摄像头采集、显示程序，QT10.0以上环境可用，原装代码，可以进行修改加以使用，如使用到倒车影像系统中，视频显示等。(tPad DE2-115/70 development board available cameras capture, display program, QT10.0 over the environment is available, the original code can be modified to be used, such as the use of the reversing video system, the video display.)
- 2020-07-09 19:58:55下载
- 积分：1
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VHDL I2C模式
---------------------------------------------------------------------------
- 2022-01-25 13:58:21下载
- 积分：1
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1_061227123744
max plus的入门与应用，适合初学者对max plus ii有一个感性的认识(max plus entry and applications, suitable for beginners to the max plus ii have a perceptual awareness of)
- 2007-11-22 09:55:10下载
- 积分：1
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16*16点阵显示”北京欢迎"
提供2个VHDL程序实现键盘显示的功能，第一个是16*16点阵显示“北京欢迎”，用VHDL语言编程实现，串烧在单片机实验工具箱上，让单片机点阵键盘上依次显示“北京欢迎”的字样。另附有LED数码管循环显示0～9数字的VHDL程序 ，成功串烧后，键盘上连续显示0~9这10个数字。
- 2022-08-03 09:36:55下载
- 积分：1
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CPU
运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。(Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.)
- 2020-09-21 10:37:53下载
- 积分：1
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fpga
FPGA代码，包含地址译码模块、16位锁存器、AD片选、死区及滤除窄脉冲、过流和短路保护、解除脉冲封锁模块、PWM模块、PWM选择
(FPGA code, including the address decoder module 16 latches, AD chip select, filter out the dead and narrow pulse, overcurrent and short circuit protection, lifting the blockade pulse module, PWM module, PWM selection)
- 2015-11-18 10:47:22下载
- 积分：1
