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16bit multiplier
Verilog code to implment the 16 bits logic multiplier. The output is also 16bits including the document to describe the implement in detail .
- 2022-01-28 09:21:47下载
- 积分：1
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Roy dsd
basic verilog code on siso, piso, sipo
- 2020-06-25 18:40:01下载
- 积分：1
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shuzishizhong
这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)
- 2013-12-10 22:21:55下载
- 积分：1
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FSM_Robustness_Testing
基于有限状态机的健壮性测试研究。
关键词：健壮性测试；增强有限状态机；全球平台；安全通道协议(The Research of Robustness Testing Based on FSM)
- 2012-09-06 14:08:56下载
- 积分：1
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EnDat
ENDAT 协议说明，包括时序等详细的说明，(endat Encoder characteristics)
- 2021-05-12 22:30:02下载
- 积分：1
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mvb_altera_may-02
altera mvb fpga sopc 设计参考文档，有一定价值(mvb fpga sopc Design scheme)
- 2015-01-15 17:15:33下载
- 积分：1
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uart
Verilog UART is written in this file
- 2013-04-16 12:34:05下载
- 积分：1
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juchibo
用vhdl语言生成锯齿波，数据可自行改变(Sawtooth wave with vhdl language generation, the data can change by itself)
- 2011-12-21 19:29:51下载
- 积分：1
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fpga 按键控制数码管
按键控制数码管 八位数码管 控制0到9 共阴极数码管
- 2022-09-22 11:25:03下载
- 积分：1
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arccos
一个求反余弦的cordic算法，整个工程。包括仿真。可以直接打开。(An inverse cosine of the cordic seeking algorithms, the whole project. Including the simulation. Can be directly opened.)
- 2009-11-04 22:48:00下载
- 积分：1
