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these files are written in verilog but i am uploading in text format
these files are written in verilog but i am uploading in text format
- 2022-08-19 04:15:42下载
- 积分:1
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zhuangtai
状态机的典型饮用,可供学习模仿之用,四个状态,简单易学(State machine of the typical drinking, can be used to learn to imitate, four state, easy to learn)
- 2007-11-11 21:36:15下载
- 积分:1
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Viterbi译码器IP核,可以直接编译使用
viterbi译码器的IP核,可以直接编译使用-viterbi decoder IP core, the compiler can directly use
- 2023-01-24 09:35:04下载
- 积分:1
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VHDL语言进行,调试通
用VHDL语言编写,在MAXPLUS2下调试通过-VHDL language, debug through MAXPLUS2
- 2023-08-07 07:55:03下载
- 积分:1
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《Verilog HDL 程序设计教程》2
《Verilog HDL 程序设计教程》2-"Verilog HDL Design Guide," 2
- 2022-03-04 04:35:38下载
- 积分:1
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LDPCtest
ldpc编码器ru算法的verilog语言的完整实现,希望对您有用(ldpc encoder, RU, VERILOG,altera)
- 2021-01-07 14:08:53下载
- 积分:1
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mod3
verilog源代码,实现两种方法的模3运算。(verilog source code,to implement the calculation of mod-3 by two means.)
- 2011-12-24 10:23:40下载
- 积分:1
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Verilog_HDL源码, Verilog_HDL源码
Verilog_HDL源码, Verilog_HDL源码-Verilog_HDL source, Verilog_HDL FO
- 2022-06-21 00:23:39下载
- 积分:1
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系统设计
说明: 基于无源蜂鸣器和矩阵按键的电子琴系统设计(design of Electronic Piano System Based on Passive Buzzer and Matrix Key)
- 2020-06-21 01:20:08下载
- 积分:1
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UDP
用verilog实现的UDP协议,包括arp,udp,ip分段协议等,对于想用FPGA实现TCP/IP协议的人来说,应该会起到一定的帮助作用(Implemented with verilog UDP protocols, including arp, udp, ip fragmentation protocol, etc., who want to achieve TCP/IP protocol with the FPGA people, should play a helpful role)
- 2021-04-05 04:39:03下载
- 积分:1