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Риторика_Зачетная работа
说明: access must be conf urr arr
- 2019-05-29 20:23:53下载
- 积分:1
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基于FPGA的VHDL可以产生不同的音调,象音乐一样
基于FPGA的VHDL可以产生不同的音调,象音乐一样-based FPGA VHDL can produce different tones, like the same music
- 2022-12-09 14:55:02下载
- 积分:1
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3 稿串行 eprom 控制器
该代码使用 FSM 3 线串行 eeprom 与 fpga 的接口。它是由微芯片定义的接口。
该代码在串行 EPROM 中存储来自 ADC 的偏移量的错误。
- 2022-02-12 01:01:57下载
- 积分:1
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数字频率计
说明: 设计一简易数字频率计,其基本要求是:
1)测量频率范围0~999999Hz;
2)最大读数999999HZ,闸门信号的采样时间为1s;.
3)被测信号可以是正弦波、三角波和方波;
4)显示方式为6位十进制数显示;
5)具有超过量程报警功能。
5)输入信号最大幅值可扩展。
6)测量误差小于+-0.1%。
7)完成全部设计后,可使用EWB进行仿真,检测试验设计电路的正确性。(The basic requirements of designing a simple digital frequency meter are:
1) The measuring frequency range is 0-999999 Hz.
2) The maximum reading is 999999HZ, and the sampling time of gate signal is 1 s.
3) The measured signal can be sine wave, triangle wave and square wave.
4) The display mode is 6-bit decimal number display.
5) It has alarm function beyond range.
5) The maximum amplitude of input signal can be expanded.
6) The measurement error is less than +0.1%.
7) After completing all the design, EWB can be used to simulate and test the correctness of the circuit.)
- 2019-06-20 12:47:51下载
- 积分:1
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BPSK
说明: 八相移键控调制的Verilog程序,给出了各个子模块的程序,实现了信号调制。(Eight-phase shift keying modulation of the Verilog program, each module is given the procedures, the signal modulation.)
- 2011-02-24 13:15:15下载
- 积分:1
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本项目是基于SR和D触发器的使用vhdl.this是100正确的内容。
this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
-this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
- 2022-06-27 01:31:46下载
- 积分:1
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vhdl 加法器 vhdl 加法器
vhdl 加法器
vhdl 加法器 vhdl 加法器
vhdl 加法器-vhdl adder vhdl adder vhdl adder
- 2022-09-01 23:25:03下载
- 积分:1
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AX301
黑金FPGA助学版-tcl,包含开发板所有管脚。不需要再对板子管脚定义。AX301(Black Gold FPGA Student Edition-tcl, development board contains all the pins. No need for a board pin definitions. AX301)
- 2021-03-23 21:59:15下载
- 积分:1
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Xilinx CPLD源代码,使用XC9500系列CPLD,驱动液晶
Xilinx CPLD源代码,使用XC9500系列CPLD,驱动液晶-Xilinx CPLD source code, use the XC9500 series CPLD, LCD Driver
- 2023-03-07 15:05:03下载
- 积分:1
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fft1024
1024点fft verilog hdl(1024-point fft verilog hdl)
- 2020-09-08 20:28:02下载
- 积分:1