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VHDL实现了IIS接口程序,在Quartus II 6.0上编译通过,在板子上可以读取IIS数据...
VHDL实现了IIS接口程序,在Quartus II 6.0上编译通过,在板子上可以读取IIS数据-IIS VHDL interface procedures, the Quartus II 6.0 compiled by the board can read data IIS
- 2022-01-26 02:43:55下载
- 积分:1
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sph-original-codes
SPH的原始代码,希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)
- 2020-10-22 10:27:23下载
- 积分:1
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mult3
this is the multiplier 3 module for the reed solomon encoder
- 2009-03-23 17:22:55下载
- 积分:1
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arm7
ARM7 VERILOG源码,非常精简,3级流水线(ARM7 VERILOG source code, very streamlined, 3-stage pipeline)
- 2009-12-02 10:57:51下载
- 积分:1
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温度码到二进制吗的转换的verilogHDL代码。
温度码到二进制吗的转换的verilogHDL代码。-Temperature code to do the conversion of binary code verilogHDL.
- 2022-02-28 22:15:49下载
- 积分:1
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costas_DPSK
采用costas环进行DPSK解调的程序。输入数据速率2.4Kbps,载波频率12KHz,采样率1.6MHz, 输入数据位宽12位,快捕带为799.617Hz(Costas ring using DPSK demodulation process. Input data rate 2.4Kbps, carrier frequency 12KHz, sampling rate 1.6MHz, the input data 12 bits wide, fast catching band is 799.617Hz)
- 2014-06-09 21:50:42下载
- 积分:1
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可编程ASCII
说明: 写出13个简单的Verilog demon,适合初学者观摩学习。配合实验报告,食用更佳。(Write 13 simple Verilog demon, suitable for beginners to observe and learn. With the experimental report, it is better to eat.)
- 2020-12-28 18:59:02下载
- 积分:1
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lmf
在ISE下,FPGA产生线性调频信号,并且产生信号的参数可调(In ISE, the FPGA generates a linear frequency modulation signal, and the parameters of the signal are adjustable.)
- 2018-03-29 15:31:15下载
- 积分:1
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modelsim_ug
Mentor Graphics ModelSim User s Guide Software v6.3g
- 2010-04-18 13:30:25下载
- 积分:1
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pgaasm
is61lv25616简单的verilog程序,完成sram读写 主要是基于FPGA(EP2C8Q208I8)下的SRAM驱动(1lv25616 simple verilog program, complete sram read and w1lv25616 simple verilog program, complete sram read)
- 2017-06-19 13:08:08下载
- 积分:1