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track_version2
说明: fpga实现相关滤波算法中的CSK算法,采用仿真的方式验证结果
fpga是xilinx
仿真工具是vivado2018.2
语言是verilog(The CSK algorithm is implemented in FPGA, and the results are verified by simulation
FPGA is Xilinx
The simulation tool is vivado 2018.2
Language is Verilog)
- 2021-04-29 16:08:42下载
- 积分:1
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Regs
说明: 一个小寄存器堆,使用参数化编程,附有仿真代码,可直接在vivado(2018.2版本及以后)上运行(A small register heap, using parametric programming)
- 2019-04-03 14:19:55下载
- 积分:1
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i2c_master_ip_for_nios
i2c master ip for altera nios, add in qsys
- 2018-03-02 14:50:44下载
- 积分:1
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can-lite-vhdl-master
说明: CAN VHDL Code. Behavioral implementation of CAN bus interface.
- 2021-01-19 21:48:41下载
- 积分:1
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anjian_xd
说明: Verilog实现按键消抖,工程,已下板验证通过。(Verilog achieves keystroke jitter elimination. The project has been validated on the lower board.)
- 2020-06-19 10:40:02下载
- 积分:1
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fpga实例程序代码
关于FPGA的一些例程,包括CORDIC数字计算机的设计,RS(204,188)译码器的设计等。(Some routines on FPGA include the design of CORDIC digital computers, the design of RS (204188) decoders, etc.)
- 2018-07-21 19:08:25下载
- 积分:1
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VerilogHDL_advanced_digital_design_code_Ch4
Verilog HDL 高级数字设计源码 _chapter4(Advanced Digital Design Verilog HDL source _chapter4)
- 2007-11-27 10:10:43下载
- 积分:1
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FIR_filter
滤波器就是对特定的频率或者特定频率以外的频率进行消除的电路,被广泛用于通信系统和信号处理系统中。(Filter is a circuit that eliminates specific frequencies or frequencies other than specific frequencies. It is widely used in communication systems and signal processing systems.)
- 2020-06-21 14:00:01下载
- 积分:1
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HDMI_FPGA
该源码可基于FPGA设置多分辨率的HDMI显示,且其包含了完整的时序和端口、地址映射,可以很方便的将其移植(The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted)
- 2020-12-17 11:09:12下载
- 积分:1
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jiaotongled
该源码用vhdl语言制作了一个简单的交通灯,方便大家学习~~(The source vhdl language produced by a simple traffic light, facilitate learning ~ ~)
- 2010-11-20 14:44:36下载
- 积分:1