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rs_encoder
RS编码器的fpga实现，有TESTBench(RS encoder to achieve the fpga, and TESTBench)
- 2009-06-24 11:37:04下载
- 积分：1
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FPGA NIOS II W5500
Altera FPGA NIOS II 通过W5500芯片完成网络TCP/IP通讯。
- 2022-08-10 04:58:17下载
- 积分：1
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FPGA-H265-Encoder
H.265的FPGA实现！！使用Verilog语言开发。(H.265 FPGA implementation! Developed using Verilog language.)
- 2021-03-08 19:49:28下载
- 积分：1
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interpolate4
调制信号后4倍内插的verilog代码，用于基带成型滤波器输入数据(4 times after modulation signal interpolation verilog code, used to baseband shaping filter input data)
- 2017-04-20 15:52:09下载
- 积分：1
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UART_CESHI
基于VHDL语言的串口发送和接收程序,自己调试通过，并已经运用在工程中(Based on the serial port to send and receive procedures VHDL language, its own debugging, and has been used in the project)
- 2016-08-05 15:27:54下载
- 积分：1
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fir48
48阶FIR滤波器的verilog，包含测试文件(48-order FIR filter verilog, including test paper)
- 2021-04-14 19:58:55下载
- 积分：1
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fifo
说明： 用FPGA完成256*8的存储器的读写操作( complete reading and writing 256* 8 memory with FPGA )
- 2010-04-24 17:07:06下载
- 积分：1
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AHB_SMSS
ahb single master single slave rtl design
- 2021-04-21 11:28:49下载
- 积分：1
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NEW
Verilog投币式手机充电仪
清华大学数字电子技术基础课程EDA大作业。刚上电数码管全灭，按开始键后，数码管显示全为0。输入一定数额，数码管显示该数额的两倍对应的时间，按确认后开始倒计时。输入数额最多为20。若10秒没有按键，数码管全灭。(Verilog coin operated cell phone charger
EDA major homework of digital electronic technology foundation course, Tsinghua University. Just put on the digital tube completely extinguished, press the start button, the digital tube display is 0. Enter a certain amount, the digital tube shows the amount of double the corresponding time, according to the confirmation began countdown. The maximum amount of input is 20. If there is no button in 10 seconds, the digital tube will die out.)
- 2020-12-10 16:29:20下载
- 积分：1
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my_test_rw_pack9
基于Verilog HDL的SDRAM控制器。
实验条件：
工具：Quartus II 6.0 ,SignalTap II
FPGA：Altera Cyclone EP1C12Q240C8N
SDRAM：HY57V283220T-6(SDRAM controller based on Verilog HDL.
Experimental conditions:
Tools: Quartus II 6.0, SignalTap II
FPGA: Altera Cyclone EP1C12Q240C8N
SDRAM: HY57V283220T-6)
- 2013-01-31 11:13:26下载
- 积分：1
