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                        VHDL
                        
                          用VHDL语言实现一Mealy型时序电路,并做时序仿真和功能仿真检验正确与否。(Implement a Mealy-type sequential circuits using VHDL language, and do functional simulation and timing simulation test correct.)                         
                            - 2014-03-20 14:44:28下载
- 积分:1
 
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                        doorlock
                        
                          基于FPGA设计的电子密码锁是一个小型的数字系统,与普通机械锁相比,具有许多独特的优点:保密性好,防盗性强,可以不用钥匙,记住密码即可开锁等。(FPGA-based design of the electronic code lock is a small digital system. It has many unique advantages:good privacy and security , it do not need the key but remember password to unlock, and so on while it compare to ordinary mechanical locks.)                         
                            - 2013-12-25 21:24:41下载
- 积分:1
 
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                        VHDL-SUBWAY
                        
                          基于QuartusII环境下的地铁自动售票系统(Subway auto ticketing system based on QuartusII)                         
                            - 2011-04-20 09:35:24下载
- 积分:1
 
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                        synthesis-bandstop-filters
                        
                          本例介绍直接合成带阻滤波器的方法,n阶滤波器能实现n个传输零点(A direct synthesis technique of a new class of bandstop
coupled resonator elliptic filters is presented. Two different
coupling schemes, which both include source–load coupling are
used. The first coupling and routing scheme is the standard folded
structure used in implementing bandpass elliptic filters with
transmission zeros using resonators.)                         
                            - 2013-03-12 18:19:01下载
- 积分:1
 
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                        BPSK
                        
                          先用Matlab理论仿真,再用Verilog语言在ISE环境下编写程序,可通过手机发送指令来控制上下变频器的参数。(Firstly, we use the theory of MATLAB to simulate, and then use Verilog language to write programs in ISE environment. The parameters of up-down converter can be controlled by sending instructions from mobile phone.)                         
                            - 2020-06-19 22:40:02下载
- 积分:1
 
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                        LDPC_DECODER(matlab)
                        
                          本程序是在AWGN下的LDPC码的仿真程序,本程序优点是译码效率高,速率很快,可以仿帧数很大的图。(the decoder for LDPC under the AWGN channel)                         
                            - 2020-12-27 21:49:02下载
- 积分:1
 
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                        FPGA 的UDP实现
                        
                          FPGA 的UDP实现,能够实现ARP、IP、UDP协议。已经通过验证。                         
                            - 2022-12-13 19:55:03下载
- 积分:1
 
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                        frame_syn
                        
                          通信系统中数据的传输以帧为单位,在FPGA中帧头检测是通信系统中的一部分,该程序实现了FPGA中帧头的检测。(Transmission of data in a communication system in units of frames, the frame header is detected in the FPGA part of the communication system, the realization of the frame header is detected in the FPGA.)                         
                            - 2014-08-27 16:02:54下载
- 积分:1
 
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                        FUNCTIONALITY OF ATM
                        
                          ATM的功能工作.atmatmamtmtmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt                         
                            - 2022-01-25 21:13:03下载
- 积分:1
 
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                        汉/解码器
                        
                          应用背景执行汉明编码和解码的32bit数据。关键技术Verilog代码的执行,汉明码在单时钟周期的32位数据编码。 ;Verilog代码进行汉明编码解码和单时钟周期的32位数据纠错。 ;试验台包括验证码。 ;在artix-7 100t现场可编程门阵列测试。简化的界面。                         
                            - 2023-03-26 14:00:03下载
- 积分:1