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FPGA-DSP
FPGA数字信号处理实现原理及方法的例程(FPGA digital signal processing principle and method routines)
- 2017-05-31 10:36:17下载
- 积分：1
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dds32_1
说明： 频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)
- 2011-04-14 13:45:22下载
- 积分：1
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verilog___UART
Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)
- 2012-05-24 20:38:27下载
- 积分：1
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52_divider
多倍（次）分频器
请注意:
本例的各个源描述的编译顺序应该是:
52_divider.vhd
52_divider_stim.vhd
(Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd)
- 2009-09-04 09:52:18下载
- 积分：1
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cnt
在ise开发环境下，建立顶层模块和子模块的层次结构，其实现的功能是一个可复位课暂停开始继续的建议秒表(In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch)
- 2014-11-03 19:35:21下载
- 积分：1
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Cordic_matlab
实现自然对数运算的cordic算法的matlab浮点仿真，以及针对FPGA硬件平台的定点仿真测试(Achieve natural logarithm of cordic algorithm matlab floating point emulation, and FPGA hardware platform for fixed-point simulation testing)
- 2013-11-01 15:10:09下载
- 积分：1
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16bit-Mulitiplier-Verilog-procedure
这是一个16位乘法器Verilog程序，包括有符号位和无符号位乘法器(This is a 16-bit multiplier Verilog program, including the sign bit and no sign bit multiplier)
- 2012-12-25 11:33:48下载
- 积分：1
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BNN-PYNQ-master
在PYNQ-Z1上搭建二值神经网络(BNN)(Building two value neural network (BNN) on PYNQ-Z1)
- 2018-01-15 11:34:33下载
- 积分：1
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jjj
实现了四bit计数器的功能，使用的是VHDL语言描述(Four-bit counter, using the VHDL language description)
- 2012-12-20 10:53:46下载
- 积分：1
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dac
简易函数发生器，能产生正弦波，三角波，梯形波，方波，并且可调频率和幅度值。(Simple function generator can produce sine, triangle wave, trapezoidal wave, square wave, and the adjustable frequency and amplitude values.)
- 2011-08-28 14:11:37下载
- 积分：1
