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verilog实现基于i2s协议接口 i2s_interface
verilog实现基于i2s协议接口，在fpga上验证通过。(Verilog implements the interface based on I2S protocol and verifies it on fpga.)
- 2017-11-05 17:26:39下载
- 积分：1
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code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx
code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx-code for kcpcm3 : Describes the working of KCPCM3 embedded in picoblaze xilinx
- 2022-04-09 10:05:17下载
- 积分：1
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VHDL——如何写简单的testbench
基于VHDL的testbench编写攻略(VHDL based on the preparation of testbench Raiders)
- 2017-07-31 15:00:45下载
- 积分：1
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lunwen
一个完整的基于FPGA的IIR低通滤波器的设计方案，是一个研究生论文(master and doctor dissertation)
- 2013-05-12 20:01:14下载
- 积分：1
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alarm
闹钟设计，VHDL，源代码。闹钟设计，VHDL，源代码。(Alarm clock design, VHDL, the source code.)
- 2011-05-23 18:30:29下载
- 积分：1
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波形发生器，带TESTBENCH，
多平台
波形发生器，带TESTBENCH，
多平台
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn
-waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn
- 2023-05-18 16:15:03下载
- 积分：1
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codelock
说明： 用VHDL实现密码锁功能，用状态机实现，分管理员和用户两种功能，可分别修改密码，重置密码等。(codelock，VHDL，state)
- 2010-03-19 13:32:14下载
- 积分：1
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ZEDBOARD
说明： ZEDBOARD的管脚分配图和约束文件，包括PCB图和xdc文件(Pin assignment of ZEDBOARD)
- 2021-03-23 21:19:15下载
- 积分：1
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The source code for the Nios II development of an example, the main demonstratio...
本源码为Nios II的开发示例,主要演示Nios II的定时中断器的应用。开发环境QuartusII。
本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II interrupt timing device applications. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.
- 2022-03-20 14:56:37下载
- 积分：1
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CPU
C++获取CPU占用率，一个类和一个头文件(Gets the CPU Use rate)
- 2015-01-23 11:15:32下载
- 积分：1
