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cordic
基于cordic算法的DDS的Verilog代码。经过仿真验证，绝对可靠。(Based on cordic algorithm DDS Verilog code. Through the simulation, is absolutely reliable.)
- 2013-12-20 17:22:38下载
- 积分：1
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This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...
This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
- 2022-04-07 07:47:24下载
- 积分：1
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verilog_ad0809 cpld control
verilog_ad0809 cpld control
- 2022-03-17 13:00:05下载
- 积分：1
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用AHDL语言编写,MAXPULS开发.通信不受外部时钟速率和数据字节数目限制....
用AHDL语言编写,MAXPULS开发.通信不受外部时钟速率和数据字节数目限制.-with AHDL prepared MAXPULS development. Communications from external clock rate and restriction on the number of data bytes.
- 2022-12-17 02:20:02下载
- 积分：1
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USART1—USART1指令控制LED灯
说明： stm32f103 usart 控制led灯(STM32F103 USART control LED)
- 2020-08-20 15:37:52下载
- 积分：1
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由VHDL 语言实现的D触发器利用的是QUARTUES环境已经得到验证
由VHDL 语言实现的D触发器利用的是QUARTUES环境已经得到验证-By the VHDL language using the D flip-flop is QUARTUES environment has been tested
- 2022-05-08 21:19:33下载
- 积分：1
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4-2switch
四位拨妞开关作为输入，当输入值变化时将其转化成两位输出(The four DIP Niu switch as an input, when the input value changes, be converted into two output)
- 2012-10-12 21:12:35下载
- 积分：1
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BPSK
BINARY PHASE SHIFT KEYING
- 2014-08-20 17:35:44下载
- 积分：1
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ethernet_loopback
通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation)
- 2017-11-20 10:21:38下载
- 积分：1
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222
说明： VHDL BISS,SSI,ENDAT2.2, ENCODER
- 2020-11-24 17:46:39下载
- 积分：1
