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8832135
一个具有“百分秒，秒，分”计时功能的数字跑表，可以实现一个小时以内的精确至百分之一秒的计时。
数字跑表的显示读者可以通过编写数码管显示程序来实现，本训练只给出数字跑表的实现过程。
读者还可以通过增加小时的计时功能，实现完整的跑表功能。(A " percentage of seconds, seconds, minutes," digital stopwatch timer can be achieved within an hour of precision to the hundredth of a second time. Digital stopwatch readers can display the digital display through the preparation of procedures to achieve, given the training is only the realization of the process of digital stopwatch. Readers can also function to increase hours of time to achieve full stopwatch function.)
- 2009-04-09 13:20:35下载
- 积分：1
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设计一个可以小时、分钟、12小时或24小时和秒的时间…
设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。
实验平台：
1. 一台PC机；
2. MAX+PLUSII10.1。
Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report
- 2022-07-22 15:10:59下载
- 积分：1
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divider
verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。(verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.)
- 2011-08-29 09:12:21下载
- 积分：1
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DS1302
基于DS1302芯片的VERILOG 语言数字钟。可实现年月日时分秒显示。(DS1302 chip-based language VERILOG digital clock. Date can be achieved when every minute display.)
- 2014-06-26 15:53:06下载
- 积分：1
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Dice_game
VHDL Project for beginners. Electronic dice game. Perfect for Spartan devices.
- 2011-02-22 22:07:59下载
- 积分：1
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Verilog module containing a synthesizable CRC function
//* polynomial: (0 1 8)...
Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 8)
// * data width: 8-Verilog module containing a synthesizable CRC function
//* polynomial: (0 1 8)
//* data width: 8
- 2022-08-18 21:19:43下载
- 积分：1
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《CPLDFPGA verilog DA0832调控
verilog da0832 cpldfpga control-verilog da0832 cpldfpga control
- 2022-12-07 05:55:03下载
- 积分：1
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24小时计时时钟
说明： 实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分：1
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FPGA-basedhardwareimplementationofneuralnetworks
基于FPGA的神经网络硬件实现中的关键问题研究，适合用fpga研究神经网络的工程人员参考(FPGA-based hardware implementation of neural networks in the study of key issues for research with neural networks fpga reference works)
- 2009-04-15 05:44:09下载
- 积分：1
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FPGA开发板上实现秒表计数器功能
这是我上大三时的电子设计题目，叫秒表的功能实现。利用ISE软件进行编程，代码是VHDL语言的，可以实现时（0-9）分（0-59）秒（0-59）即最大10小时的计数，对于不同开发板，可以适当修改代码，使之成为更加广泛的计数器。代码纯原创，请下载。
- 2023-01-08 12:35:04下载
- 积分：1
