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ser_to_parr
很有用的10bit串并转换verilog程序，需要的可以拿去参考下，在quartusII上已验证过(Useful 10bit string and convert verilog program, need to take a reference, has been verified in quartusII)
- 2012-05-21 16:21:22下载
- 积分：1
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uart766
---实现的部分VHDL 程序如下。
--- elsif clk1x event and clk1x = 1 then ---if std_logic_vector(length_no) >= “0001” and std_logic_vector(length_no) <= “1001” then -----数据帧数据由接收串行数据端移位入接收移位寄存器---rsr(0) <= rxda --- rsr(7 downto 1) <= rsr(6 downto 0) --- parity <= parity xor rsr(7) --- elsif std_logic_vector(length_no) = “1010” then --- rbr <= rsr --接收移位寄存器数据进入接收缓冲器--- ...... --- end if(--- achieve some VHDL procedure is as follows.--- Elsif clk1x event and then a clk1x = s--- if td_logic_vector (length_no))
- 2007-06-02 12:44:31下载
- 积分：1
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chengxu
设计制作一个可容纳4组参赛者的数字智力抢答器，每组设置一个抢答按键；
电路具有一第一抢答信号的鉴别和锁存的功能。在主持人将系统复位并发出抢答指令后，若参加者按抢答键，则该组指示灯亮并用组别显示抢答者的组别。此时，电路具有自锁功能，使别组的抢答开关不起作用。
设置计分电路。每组在开始时预置成6分，抢答后主持人计分，答对一次加1分。(The design can accommodate a the Entrants digital intellectual Responder, each set answer in a key circuit has a first answer in the signal to identify and latch functions. Host to the system reset and sent the answer in instruction, participants answer in key, the group of the group light and display the answer in the group. At this point, the circuit has a self-locking function does not work in other groups to answer switch. Set Scoring circuit. Preset six points each at the beginning of the answer in scoring after the host, answer time, add 1 point.)
- 2012-06-10 12:58:44下载
- 积分：1
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qiangdaqi
本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)
- 2013-10-30 14:48:21下载
- 积分：1
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CPU
不同方法实现的CPU系统。同样支持加减乘，逻辑/算术移位，与或非等建议指令。(Different methods to achieve CPU system. Also supports, subtraction, multiplication, logic/arithmetic shift, and the like or recommend instruction.)
- 2016-04-16 20:30:51下载
- 积分：1
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gtwizard_254_127_ex_1113_3
配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)
- 2019-06-17 21:33:56下载
- 积分：1
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AXI协议的slave的verilog实现
AXI（Advanced eXtensible Interface）是一种总线协议，该协议是ARM公司提出的AMBA（Advanced Microcontroller Bus Architecture）3.0协议中最重要的部分，是一种面向高性能、高带宽、低延迟的片内总线。它的地址/控制和数据相位是分离的，支持不对齐的数据传输，同时在突发传输中，只需要首地址，同时分离的读写数据通道、并支持Outstanding传输访问和乱序访问，并更加容易就行时序收敛。AXI 是AMBA 中一个新的高性能协议。AXI 技术丰富了现有的AMBA 标准内容，满足超高性能和复杂的 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报
- 2022-07-20 13:16:27下载
- 积分：1
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FPGA 的UDP实现
FPGA 的UDP实现，能够实现ARP、IP、UDP协议。已经通过验证。
- 2022-12-13 19:55:03下载
- 积分：1
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led_water
酷睿系列流水灯通用程序，来回往返流水，点亮led(ledwater for ep2c8q208c8)
- 2017-11-11 00:57:15下载
- 积分：1
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20190717 - Copy
说明： this describes building spi block on verilog hdl and programming them on an fpga device
- 2020-06-21 21:40:02下载
- 积分：1
