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data_swith
verilog 代码实现串并转换，有延迟(Verilog code and string conversion, delay)
- 2011-07-31 23:58:17下载
- 积分：1
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7941952NCO_sin
NCO 代码设计 使用VHDL语言 (nco)
- 2009-05-23 16:39:37下载
- 积分：1
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SPI_test
用FPGA于32进行SPI单向通信，FPGA向32放松发送数据(One-way SPI communication is carried out in 32 with FPGA, and data is sent to 32 with ease by FPGA.)
- 2020-06-18 10:40:02下载
- 积分：1
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QPSK_demod
说明： QPSK的解调程序，采用Verilog编写而成(QPSK demodulation program, written by Verilog)
- 2020-02-29 19:51:38下载
- 积分：1
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W5100
使用spi模式初始化w5100，实现了快速以太网的初步建立(Using the spi mode initialization w5100, to achieve the initial establishment of a Fast Ethernet)
- 2020-08-02 20:08:35下载
- 积分：1
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uart
uart 发送模块接收模块及tb，其中可以选择不同波特率进行收发，代码带有详细注释。(UART sending module and receiving module)
- 2020-06-20 20:00:02下载
- 积分：1
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AES加密算法verilog源码
AES加密算法verilog源码
This project is the hardware implementation of the
Advanced Encryption Standard with a key size of 128 bits.
The implementation adheres to the FIPS-197 document which explains the same.The core can do both encryption as well as decryption.The documents aes_arch.doc and aes_tb_readme.txt give further details of the rtl implementation and test bench respectively. This code was written originally with 128 bit ports for both input and key but later converted to 64 bits each to save on i/o pins. It can be reverted back easily if one just changes the port widths and dispenses with the load signal in the top module and making approriate changes in process where load is used.Synthesis results have been included for Xilinx Spartan-3 device.The directory structure of the project is as under-
AES128
- 2023-05-16 03:30:03下载
- 积分：1
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四位全加器的Verilog源代码
应用背景小的verilog程序，实现一四位全加器的功能。它有两大模块。一个是四位全加器，另一个是一位全加器，它是采用组合逻辑，不复杂，但简洁明了。这将是一个很好的第一步，学习verillog。适合初学者练习。关键技术只是Verilog和组合逻辑实现一四位加法器。它建立了2个模块。一个是大 ；框架，其他作品如子功能。家庭 ；spratan-3e XC3S100E，设备，包装cp132。全加器意味着它有一个进位，它可以显示的进行，如果过流发生。
- 2022-02-07 21:27:28下载
- 积分：1
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awb
自动白平衡的verilog实现
通过逻辑实现了白平衡算法(awb design awb design awb design awb design awb design )
- 2012-09-04 13:09:50下载
- 积分：1
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code
浙江大学体系结构实验代码 实现流水线的forwarding(Architecture, Zhejiang University Experimental code pipeline forwarding)
- 2020-09-26 11:57:46下载
- 积分：1
