登录
首页 » VHDL » UART异步串行通信协议的源代码,采用VHDL语言…

UART异步串行通信协议的源代码,采用VHDL语言…

于 2022-03-20 发布 文件大小:10.75 kB
0 182
下载积分: 2 下载次数: 2

代码说明:

uart异步串口通信协议的源代码,用vhdl语言编写,并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • e_BIU
    说明:  isa MEMORY PLAN eu biu asm
    2020-06-25 19:20:02下载
    积分:1
  • xc3s400芯片详细的英文资料,xc3s400的FPGA开发板使用者必看
    xc3s400芯片详细的英文资料,xc3s400的FPGA开发板使用者必看-chip xc3s400 detailed information in English, xc3s400 the FPGA development board users see
    2023-09-02 13:00:04下载
    积分:1
  • 一些vhdl的简单例子。直接解压,不用密码。
    一些vhdl的简单例子。直接解压,不用密码。-instantiate some simple examples. Direct unpack, without a password.
    2023-04-21 21:55:02下载
    积分:1
  • 基于VHDL的I2C程序0002,很不错的论文及程序,,大家快下啊
    基于VHDL的I2C程序0002,很不错的论文及程序,,大家快下啊-based on the I2C procedures VHDL 0002, a very good paper and procedures, we quickly under ah
    2022-03-24 23:26:37下载
    积分:1
  • verilog实现ALU的源代码,并提供了详细的测试平台!
    verilog实现ALU的源代码,并提供了一个详细的测试平台!-achieve ALU Verilog source code, and provide a detailed test platform!
    2022-03-15 13:01:46下载
    积分:1
  • EMIF
    EMIF接口调试代码,使用的是Verilog语言,FPGA与DSP通信,测试成功(EMIF interface debugging code that USES the Verilog language, FPGA and DSP communication, testing success)
    2020-12-04 10:39:24下载
    积分:1
  • m_ca7
    verilog编写的基于CA算法的m序列发生器,其中验证了多种CA系数来实现m序列。(CA-based algorithm written in verilog m-sequence generator, which verify the CA factor to achieve a variety of m-sequence.)
    2011-10-26 14:33:59下载
    积分:1
  • rom_fft
    采用xilinx的ROMIP核产生类似正弦信号,经过FFt后可以观察结果(Using the xilinx ROMIP nuclear generating similar sinusoidal signal can be observed through the results after FFt)
    2013-09-14 20:59:03下载
    积分:1
  • stm32adc12路采集DMA
    说明:  adc采集多路采集多通道基于dma的adc采集(ADC acquisition, multi-channel acquisition and multi-channel acquisition)
    2020-06-19 06:20:01下载
    积分:1
  • taxi
    利用Verilog HDL语言设计了出租车计费器,使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能,并设置了动态扫描电路显示车费和对应时间,显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。(Design using Verilog HDL language a taxi meter, it has time display, billing and simulation taxi start, stop, reset and other functions, and set dynamically display scanning circuit and the corresponding time fare, shows the hardware description language Verilog-HDL design advantages of digital logic circuits.)
    2011-08-30 08:18:51下载
    积分:1
  • 696518资源总数
  • 106164会员总数
  • 18今日下载