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HDB3modelsim
HDB3编码通过verilog实现,通过modelsim仿真(HDB3 coding is implemented by Verilog and simulated by Modelsim)
- 2020-06-18 05:20:02下载
- 积分:1
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Verilog_HDL
华为文档《硬件描述语言Verilog基础》-目录
原来搞VHDL,刚刚开始学Verilog。觉得这个入门的提纲不错,共享一下。
(Huawei Documents " basic Verilog Hardware Description Language" - the original directory engage in VHDL, just beginning to learn Verilog. Feel that the entry of the outline of a good, share some.)
- 2009-02-21 18:02:37下载
- 积分:1
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tcpip_stack_v1_2
说明: 实现ARP、ICMP、UDP、TCP、IP和MAC全过程的传输,对TCP的连接、接收、发送、断开均经过测试,功能正常(Realize the transmission of ARP, ICMP, UDP, TCP, IP and MAC in the whole process, test the connection, reception, transmission and disconnection of TCP, and the function is normal)
- 2020-05-05 10:03:04下载
- 积分:1
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键盘按键消抖
键盘按键消抖,短时间内的摁键键值采集,在规定时间内,如果存在按键的上升沿和下降沿,不予以采集,超过该时间,则采集为该键当前状态值
- 2022-08-10 06:33:27下载
- 积分:1
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速率发生器
这个程序是用来划分时钟,实现9600个传输速率的。该代码是在10兆赫的时钟频率运行。它计算特定的传输速率所需的比特数;
- 2022-08-22 03:09:34下载
- 积分:1
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DAC_VHDL
DAC VHDL code using SPI method
- 2016-11-09 19:53:01下载
- 积分:1
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zongbian4
基于verilog语言的差分曼彻斯特编码,内包含数据的采集,CRC校验(8位),和编码,输出。附有完整的工程文件。可直接调用modelsim仿真。(Based on differential Manchester encoding verilog language, and contains data collection, CRC check (8), and coding. With complete project file. Modelsim simulation can be called directly.)
- 2021-03-04 09:59:32下载
- 积分:1
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fifo
同步fifo,本设计采用同步fifo方式,中间例化ram,实现同步fifo传输
- 2022-10-13 12:40:03下载
- 积分:1
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freq
vhdl八位十进制数字频率计的设计,顶层和数码管扫描模块(vhdl eight decimal digital frequency meter design, top-level and digital tube scanning module)
- 2012-10-09 15:09:22下载
- 积分:1
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traffic-light
Traffic light program in c presents what happens in our daily life at traffic light signals.
- 2012-11-06 06:50:15下载
- 积分:1