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单相逆变simulink仿真
说明： 利用Matlab/simulink实现电力仿真，其中单相逆变可用于多电平变流器的基础使用，本案例提供了不同调制手段实现逆变的模型(Matlab / Simulink is used to realize power simulation, in which single-phase inverter can be used as the basis of multi-level converter. This case provides the inverter model with different modulation means)
- 2019-11-12 15:03:55下载
- 积分：1
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progconterful
four bit counter verlog source code for veriwell including test bench
- 2010-03-29 18:54:45下载
- 积分：1
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rs-decoder-make-byvhdl
- RS码是Reed-Solomon 码（理德－所罗门码）的简称，它是一类非二进制BCH码，在RS码中，输入信号分成k·m比特一组，每组包括k个符号，每个符号由m个比特组成。(- RS code is a Reed-Solomon code (Reed- Solomon codes) for short, is a non-binary BCH code, the RS code, the input signal is divided into a set of k · m bits, each including k symbols, each symbol consists of m bits.)
- 2021-04-28 15:58:44下载
- 积分：1
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RS_coder
基于verilog的RS编码器 绝对实用(Based on the RS encoder verilog absolute utility)
- 2010-12-07 20:51:02下载
- 积分：1
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SERDES_handbook
SERDES资料，包括reliability_handbook,serdes_handbook,serdes_introduction(SERDES doc,include reliability_handbook,serdes_handbook,serdes_introduction)
- 2017-01-12 18:28:41下载
- 积分：1
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cpu_design
FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告(FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language)
- 2020-12-03 13:09:25下载
- 积分：1
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UART module Verilog codes and guidance
Verilog codes of UART modules and guidances of UART
- 2022-05-19 07:09:53下载
- 积分：1
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A-Memristor-SPICE-Model
一篇讲述如何在pspice软件中仿真忆阻器（memristor）替代蔡氏混沌电路中的非线性电阻进而观察研究混沌相图的文献(How about a software simulator pspice memristor (memristor) alternative Chua' s chaotic circuit chaotic nonlinear resistance and then observe the phase diagram of the literature)
- 2011-11-17 16:04:55下载
- 积分：1
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shift_regeister
用blockram实现移位寄存器，开发语言为verilog hdl(Shift register with blockram achieve the development language for the verilog hdl)
- 2020-08-13 22:18:29下载
- 积分：1
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spi
VHDL实现SPI功能源代码
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- slave shift their shift registers 8 bits and thus exchange their 8
-- bit register values.(SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the )
- 2021-04-29 10:58:43下载
- 积分：1
