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EPM570
非常好的EPM570(CPLD)学习程序源码,适合初学者,能让其快速入门(Very good EPM570 (CPLD) learning program source code, suitable for beginners, allowing its Quick Start)
- 2013-09-11 10:18:59下载
- 积分：1
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20181060261-李康_3
说明： 秒表的实现，有暂停清零功能，Quartus II(Stopwatch realization, has the pause clear function)
- 2020-12-26 15:56:03下载
- 积分：1
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pc_cfr_test_v3_1c
一个关于降低现代通信系统中高峰均比信号的matlab算法，对于研究数字预失真基于FPGA实现的有一定作用！(A modern communication system on the lower than the peak signal matlab algorithm for FPGA-based study of digital pre-distortion to achieve a certain effect!
)
- 2011-07-07 22:01:17下载
- 积分：1
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FIR
本实验主要是在FPGA上实现FIR数字滤波器的功能，不仅有工程文件，还具有论文资料。(This experiment mainly realizes the function of FIR digital filter on FPGA, not only has the engineering document, but also has the thesis information.)
- 2020-10-05 11:27:38下载
- 积分：1
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16位元浮点数CPU,可作运算,以VHDL编写
16位元浮点数CPU,可作运算,以VHDL编写-16-bit floating point CPU, can be used for computing in order to prepare VHDL
- 2022-05-17 06:20:07下载
- 积分：1
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sim_uart
uart 收发器 verilog 代码，实现自收发功能
sys clk = 25m, baud 9600 停止位1， 无校验位；
代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过；
(verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )
- 2010-10-10 21:49:46下载
- 积分：1
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VHDL语言实现摄像头的捕捉和采集,通过仿真验证，很好哈
VHDL语言实现摄像头的捕捉和采集,通过仿真验证，很好哈-vidicon s catch and collection in VHDL
- 2022-09-22 03:05:04下载
- 积分：1
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costas_BPSK
说明： 文档科斯塔斯环路滤波器。。。。。般若撒根本(wendangsafwrfgvearbeabf)
- 2019-10-29 20:06:34下载
- 积分：1
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digital_clock
数字钟通过verilog实现，并且支持Modelsim仿真，通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)
- 2020-06-18 05:00:02下载
- 积分：1
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UC1676C
51单片机测试程序，ＩＣ:UC1676,4线串口(51 MCU test program, IC:UC1676 4-LINE, SPI INTERFACE)
- 2020-10-17 11:17:28下载
- 积分：1
