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Sdram_Control_4Port
使用verilog HDL写的sdram(SDR)的控制器源代码，具有很好的可移植性，试验的例子已经通过QuartusII 9.0编译通过，可以运行在cycloneII上(Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII)
- 2012-05-14 15:36:09下载
- 积分：1
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LPC总线从设备的verilog设计,包含状态机和中断功能。
LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device
- 2022-01-28 17:10:12下载
- 积分：1
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DE2_115_Synthesizer
FPGA implementation of simple Multi-tone Electronic Keyboard using DE2-115 board with a PS/2 keyboard and speaker
- 2013-08-20 19:48:32下载
- 积分：1
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ADAPTIVEFILTER
采用vhdl代码描述自适应滤波器，具有很好的可参考性，和实用性(Vhdl code to describe the use of adaptive filter, can be found with a good nature and usefulness of)
- 2010-02-05 23:37:48下载
- 积分：1
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ComChange-12061629
说明： 并行读写14路串口数据，数据被写入FIFO，在收到读写信号后，SPI发送数据出去(Parallel read and write 14 serial port data, SPI send data)
- 2019-03-13 01:38:44下载
- 积分：1
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Coding Files
Floating Point FP multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double precision multiplier is implemented on a Virtex 6 FPGA. In addition, the proposed design is compliant with IEEE 754 format and handles over flow, under flow, rounding and various exception conditions. The design achieved the operating frequency of 414.714 MHz with an area of 648 slices.
- 2017-12-13 23:58:23下载
- 积分：1
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verilog
lap of altera . it s basic about verilog
- 2010-06-25 20:30:32下载
- 积分：1
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cla - Copy
ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER
- 2019-03-19 01:35:37下载
- 积分：1
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SMBus
SMBus控制器的VHDL源码程序，适用于Quartus2，ISE等开发环境。(The SMBus controller VHDL source code procedures applicable to Quartus2 ISE development environment.)
- 2021-03-24 18:39:14下载
- 积分：1
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keyscan
用verilog语言写的简单的键盘扫描代码，适合初学者，用alter的软件编写的程序代码。(Using verilog language to write simple keyboard scan code, suitable for beginners, with alter software program written code.)
- 2013-09-13 22:59:11下载
- 积分：1
