-
chuankou_huihuan
FPGA与PC端实现串口数据的收发，先从PC端接收数据，然后发回给电脑，可通过串口助手验证。(The serial port data is sent and received between the FPGA and the PC. First, the data is received from the PC, and then sent back to the computer. It can be verified by the serial port assistant.)
- 2020-06-16 10:20:01下载
- 积分：1
-
integer_chao_fpga
通过FPGA实现整数阶混沌系统，通过定点数的方式，全并行。(The realization of integer order chaotic systems through FPGA)
- 2021-02-20 22:49:43下载
- 积分：1
-
I2C Verilog
应用背景你好这是一个verilog代码^ _ ^这是一个verilog代码^ _ ^这是一个verilog代码^ _ ^这是一个verilog代码^ _ ^关键技术Verilog对我很好Verilog对我很好Verilog对我很好Verilog对我很好Verilog对我很好Verilog对我很好Verilog对我很好
- 2022-01-25 16:40:39下载
- 积分：1
-
VLSIrtl_spi
说明： verilog语言写的SPI接口,全同步设计,低门数,可以很容易应用到嵌入设计方案中.(Verilog language to write the SPI interface, all synchronous design, low gate count. it is very easy to use embedded design programs.)
- 2021-05-13 13:30:02下载
- 积分：1
-
LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
- 2013-07-25 14:43:43下载
- 积分：1
-
ass1_3_safe
The objective of this project is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last
- 2011-03-05 01:17:22下载
- 积分：1
-
vvgzkcao
非常需要的可以下载看看,适合初学者学习,好的算法和程序(Very need to download to see, suitable for beginners to learn, good algorithm and program.)
- 2018-10-07 12:53:09下载
- 积分：1
-
Риторика_Зачетная работа
access must be conf urr arr
- 2019-05-29 20:23:53下载
- 积分：1
-
lovesh
NN CONTROLLER FOR UPQC
- 2012-11-12 14:01:31下载
- 积分：1
-
buffer
用verilog实现的buffer，经过了fpga平台验证。(Implement buffer with verilog.)
- 2020-10-28 12:19:58下载
- 积分：1
