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ps2
PS2键盘硬件模块控制器，主要实现硬件PS2键盘的控制，适合初学verilog学者实验。(PS2 keyboard controller hardware module, the main hardware PS2 keyboard control, suitable for beginners verilog scholar experiments.)
- 2014-09-16 19:06:23下载
- 积分：1
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用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS
用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS--use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-
- 2022-07-22 06:50:26下载
- 积分：1
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IEEE 802.3 Cyclic Redundancy Check参考设计，xilinx提供
IEEE 802.3 Cyclic Redundancy Check参考设计，xilinx提供-IEEE 802.3 Cyclic Redundancy Check reference design for Xilinx
- 2023-02-15 07:55:03下载
- 积分：1
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DWT-VHDL
小波变换的VHDL代码，内带正变换逆变换的测试文件。(Wavelet transform VHDL code, with a positive transformation within the inverse transform of the test file.)
- 2010-05-14 20:37:27下载
- 积分：1
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verilog HDL语言编写的键盘扫描程序，考虑以确定关键的博…
Verilog HDL编写的键盘扫描程序，考虑了判断按键弹起的问题。程序按一定的频率用低电平循环扫描行线，同时检测列线的状态，一旦判断有一列为低则表示有键被按下，停止扫描并保持当前行线的状态，再读取列线的状态从而得到当前按键的键码；等待按键弹起：检测到各列线都变成高点平后，重新开始扫描过程，等待下一次按键。-Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. Program according to a certain frequency of scan lines with low-level circulation lines, while testing out the state line, once the judge has said there is a classified as low-key is pressed, stop the scan and to maintain the current line-line state, and then read out line state to get the current keys key codes to wait for key pop-up: To detect the lines at all out into a high level after the re-start the scanning process, waiting for the next key.
- 2022-05-07 15:33:47下载
- 积分：1
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verilog program for iic bus design. the pakege includes iic protocl master progr...
Verilog数字系统设计教程【夏宇闻】原书第十章：IIC总线接口模块设计代码包-verilog program for iic bus design. the pakege includes iic protocl master program and behavel slavle program, even includes testbench and data bat files.
- 2022-01-31 13:13:45下载
- 积分：1
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mux8to1_with_if
this code to input 8 different data and make them out sequentialy
- 2015-02-19 10:54:20下载
- 积分：1
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48_4.12
网络通信中的MII接口
通常将4位nibble数据送出，此程序将4位数据组合成8位数据并行输出（8比特==1个字节）。。完全可用
同时包含84转换(The MII network interface usually sent four nibble data, this procedure will be 4-bit data into 8-bit parallel output data (8 bits == 1 byte). . Completely available at the same time contains 84 conversion)
- 2009-04-21 13:43:45下载
- 积分：1
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MUX
Multipleksor
3 to 1 - 3x1bit in, 1x1bit out
- 2013-09-18 16:21:25下载
- 积分：1
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these files are written in verilog but i am uploading in text format
these files are written in verilog but i am uploading in text format
- 2022-08-19 04:15:42下载
- 积分：1
