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ISE
设计一4位比较器,画出门级电路图,用verilog语言完成设计。
(Design a four comparators, drawing out level circuit diagram, complete the design using verilog language. )
- 2015-12-11 21:16:12下载
- 积分:1
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wimax_ofdm-master
wimax ofdm系统评估代码 wimax ofdm system code 很有参考价值(wimax ofdm system code)
- 2018-11-15 16:35:20下载
- 积分:1
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debounce
FPGA按键延时模块,产生key_value和key_flag
可直接例化调用(The key delay module of FPGA)
- 2020-06-22 04:20:02下载
- 积分:1
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tcpip_stack_v1_2
说明: 实现ARP、ICMP、UDP、TCP、IP和MAC全过程的传输,对TCP的连接、接收、发送、断开均经过测试,功能正常(Realize the transmission of ARP, ICMP, UDP, TCP, IP and MAC in the whole process, test the connection, reception, transmission and disconnection of TCP, and the function is normal)
- 2020-05-05 10:03:04下载
- 积分:1
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CH372
USB设备接口的驱动程序,采用verilogHDL语言编写,并包含相关说明资料(USB device driver interface, using verilogHDL language, and contains descriptive information)
- 2014-01-03 02:23:08下载
- 积分:1
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01_基于ZYNQ的FPGA基础入门
VIVADO SOC 使用文档 基于zynq 7020(vivado soc example text of zynq)
- 2020-06-17 12:00:01下载
- 积分:1
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xj2
基于FPGA,利用VHDL语言对小车循迹进行设计。(Car tracking)
- 2011-11-01 22:36:25下载
- 积分:1
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一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码
一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码-VerilogHDL language based on the 16-bit multiplier of the booth algorithm and test code
- 2022-02-07 12:03:36下载
- 积分:1
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shiyan5
应用布莱克曼窗实现FIR滤波器,并绘制相应波形图案(Application Blackman window FIR filter, and draw the corresponding waveform pattern)
- 2014-01-09 11:50:49下载
- 积分:1
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lab7_files
关于Digilent Atlys Spartan-6 FPGA development board audio ac97的讲解及具体应用的源码(Digilent Atlys Spartan-6 FPGA development board audio of ac97' s presentation as well as the specific application' s source code)
- 2013-02-01 11:02:38下载
- 积分:1