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multifreqvhdl
说明： 资料是本人根据相关文献资料用vhdl语言编写的旋转机械鉴相信号倍频的程序，multifre1.vhd是倍频程序，multifre1.vwf是仿真波形文件，stp1.stp是虚拟逻辑分析仪signaltap文件。该倍频程序可以直接使用，可以设置倍频数，修改实体参数N即可。(According to the literature data is the information I have written in with vhdl Rotating Machinery Kam believe that the procedure multiplier number, multifre1.vhd is the multiplier process, multifre1.vwf is the simulation waveform files, stp1.stp a virtual logic analyzer signaltap file. The multiplier process can be used directly, you can set the multiplier number, modify the parameter N can be solid.)
- 2010-04-26 16:05:18下载
- 积分：1
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formal_verification
说明： 现在最流行的RTL设计方法之一，本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)
- 2020-06-23 22:00:02下载
- 积分：1
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tcoug
Synopsys®
Timing Constraints and Optimization
User Guide
- 2014-08-23 17:37:56下载
- 积分：1
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src
说明： 假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 + 寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)
- 2020-12-15 13:49:14下载
- 积分：1
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VHDL digital system design and engineering practice, one that contains principle...
VHDL数字系统设计和工程实践2，包含原理，真值表和原理图，以及VHDL源代码.-VHDL digital system design and engineering practice, one that contains principles, truth table and schematic, as well as VHDL source code.
- 2022-02-11 12:04:45下载
- 积分：1
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波形发生器，用于编写testbentch文件。非常实用
波形发生器，用于编写testbentch文件。非常实用-Waveform generator, for the preparation of testbentch files. Useful
- 2022-10-22 19:55:04下载
- 积分：1
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MODELSIM开发的模拟CPU，用VHDL语言描述，采用累加结构
MODELSIM开发的模拟CPU，用VHDL语言描述，采用累加结构-ModelSim simulation developed CPU, using VHDL language description of the structure of the use of cumulative
- 2022-02-07 08:56:30下载
- 积分：1
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spdif_interface_latest.tar
音频spdif格式编解码，可以将音频格式在i2s dsd以及spdif之间转换(Spdif audio codec)
- 2016-05-15 11:02:34下载
- 积分：1
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用VerilogHDL编写的，一个占空比为50％的6分频电路
用VerilogHDL编写的，一个占空比为50％的6分频电路-prepared using Verilog HDL, a 50% duty cycle for the six sub-frequency circuit
- 2023-06-23 12:25:03下载
- 积分：1
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基于任意波形发生器的实现可编程逻辑器件…
基于可编程逻辑器件实现任意波形发生器VHDL源代码-Programmable logic device based on the arbitrary waveform generator implementation VHDL source code
- 2023-05-09 22:45:03下载
- 积分：1
