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LED
一个走马灯的程序,可以按照要求一个一个往后面按顺序点亮(A program for the lantern can be lit one by one according to the requirements.)
- 2019-06-28 15:18:09下载
- 积分：1
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Arty-Z7-20-hdmi-out-master
说明： Arty Z7 20 HDMI output
- 2021-04-24 15:18:47下载
- 积分：1
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CODE_VHDL_INITIALIZING 液晶电视 DISPLAY(KHỞI TẠO HIỂN THỊ LCD)
CODE_VHDL_INITIALIZING 液晶电视 DISPLAY(KHỞI TẠO HIỂN THỊ LCD)
- 2022-03-17 18:12:45下载
- 积分：1
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ep2c5 实现 定时器
verilog语言，quartus 2 仿真
ep2c5 实现 定时器
verilog语言，quartus 2 仿真-verilog language to achieve ep2c5 timer, quartus 2 Simulation
- 2022-09-22 03:15:03下载
- 积分：1
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DDS的频率转换可以以近似认为是即时的，这是因为它的相位序列在时间上是离散的，在频率控制字改变之后，要经过一个时钟周期之后才能按照新的相位增量增加，所以也可以说...
DDS的频率转换可以以近似认为是即时的，这是因为它的相位序列在时间上是离散的，在频率控制字改变之后，要经过一个时钟周期之后才能按照新的相位增量增加，所以也可以说它的频率转换时间就是频率控制字的传输时间，-DDS frequency conversion can be considered similar to real-time, this is because it is the phase sequence in time is discrete, in the frequency control word change after one clock cycle to go through before a new phase in accordance with the incremental increase, so it can be said of the frequency switching time is the frequency control word transmission time,
- 2022-02-13 18:40:44下载
- 积分：1
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Verilog版的C51核(OC8051)
Verilog版的C51核(OC8051)-Verilog version of the C51 core (OC8051)
- 2022-04-30 06:36:25下载
- 积分：1
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Verilog实现 spi接口的FPGA实现 通过仿真，修改后即可应用
Verilog实现 spi接口的FPGA实现 通过仿真，修改后即可应用-Verilog realize spi interface FPGA to achieve through the simulation, the application can be modified
- 2022-08-14 13:03:16下载
- 积分：1
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h264_intp
图形图像H264插值算法，应用于图像视频处理(H264 graphic image interpolation algorithm is applied to image video processing)
- 2021-05-14 18:30:02下载
- 积分：1
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chuankou
本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分：1
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procedures major hardware description language (VHDL) to achieve : MCU and FPGA...
程序主要用硬件描述语言（VHDL）实现：
单片机与FPGA接口通信的问题-procedures major hardware description language (VHDL) to achieve : MCU and FPGA interface communication problems
- 2022-02-12 01:14:15下载
- 积分：1
