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PCIE
xilinx spartan6的pcie pio源代码(xilinx spartan6 pcie pio demo)
- 2020-11-25 14:39:32下载
- 积分：1
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h_adder
ise13.2环境下VHDL编写的半加器器+仿真波形(ise13.2 environment half adder in VHDL simulation waveform control+)
- 2013-06-01 13:40:03下载
- 积分：1
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在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意...
在QuartusII下进行编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意-QuartusII warning solving
- 2022-03-01 12:03:29下载
- 积分：1
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MP3-coder
In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder.
Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read the output or input 576 frequency lines.(This folder contains three directories: Huffman, IMDCT and Filterbank, each of them
includes all the VHDL source codes of the component.)
- 2013-08-06 15:40:24下载
- 积分：1
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这是个vhdl编写的16bit的加减法器
这是个vhdl编写的16bit的加减法器-This is vhdl prepared by the modified instruments used in the 16bit
- 2022-02-15 07:17:54下载
- 积分：1
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router_routing
片上网络NOC基于fpga实现的，routing模块。(NOC-chip networks realized fpga-based, routing module.)
- 2021-03-03 17:19:32下载
- 积分：1
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DDS
说明： 使用Verilog，以Quartus II 为平台，编写了一个DDS信号发生器程序。(Using Verilog and Quartus II as the platform, realizing the DDS signal generator program .)
- 2020-11-26 17:12:26下载
- 积分：1
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vhdl um teste com muita coisa interessante ae pra ver
vhdl um teste com muita coisa interessante ae pra ver
- 2023-07-05 20:40:02下载
- 积分：1
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Using VHDL realize the divider, so very, simulation adopted
用VHDL实现的除法器,非常好使,仿真通过了-Using VHDL realize the divider, so very, simulation adopted
- 2023-06-11 22:15:03下载
- 积分：1
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coverlater
本程序是在Quartus7.2环境下编译的一个简单的(2,1,3)卷积码，能够成功地编译和仿真。(This procedure is in circumstances Quartus7.2 compile a simple (2,1,3) convolutional code, can successfully compile and simulation.)
- 2021-03-13 20:49:24下载
- 积分：1
