本例程位于 VMD642_CPLD目录中。 使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使 用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)

说明：  这是一个关于OQPSK的Matlab程序 这是一个关于OQPSK的Matlab程序 (This is a OQPSK the Matlab program is a program of OQPSK in Matlab)

《数字信号处理的FPGA实现（第三版）》作者：U.Meyer-Baese 的配套源码，基于quartus9.0编写，使用的cyclone ii。其中包含FIR IIR FFT等算法的实现，对学习图像处理很有帮助。( FPGA digital signal processing (third edition) Author: U.Meyer-Baese The matching source, based on quartus9.0 preparation, the use of cyclone ii. Which includes FIR IIR FFT algorithm such as the realization of learning to image processing helpful.)

TASKS OF TWO TYPES CAN BE RUN FOR EVERY 2 MIN.

FPGA实验_HDB3编码器设计(包含5个模块)(FPGA design experiments _HDB3 encoder (including 5 modules))

偶数分频，包括验证程序，verilog实现，可综合-Even-numbered sub-frequency, including the verification process, verilog realize, can be integrated

一共7篇文章，介绍了使用fpga产生任意分布白噪声的方法，值得借鉴(A total of seven articles, describes using fpga to generate arbitrary distribution of white noise, it is worth learning)

该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)

这是由阿龙利开发的程序，以控制ADC08D1000模拟 - 数字设备中的FPGA，赛灵思的Virtex-4 SX35 FPGA此处应用，DCM的用于控制FPGA中的时钟路径，所述时钟源是AD9517该PLC控制的FPGA中的串行端口

ES A PRACRICA 2 DEL LABORATORIO DE DIGITAL