-
fpga0023202323
FPGA时序分析说明。对于高速时钟设计中的时序分析与约束有帮助(FPGA,TIME)
- 2010-11-01 15:49:34下载
- 积分:1
-
设计一个可以小时、分钟、12小时或24小时和秒的时间…
设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟,并具有定时与闹钟功能,能在设定的时间发出闹铃音,能非常方便地对小时、分钟和秒进行手动调节以校准时间,每逢整点,产生报时音报时。
实验平台:
1. 一台PC机;
2. MAX+PLUSII10.1。
Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report
- 2022-07-22 15:10:59下载
- 积分:1
-
使用VHDL编写的分频程序,能进行任意次的偶数分频,程序简单易懂,供
初学者参考...
使用VHDL编写的分频程序,能进行任意次的偶数分频,程序简单易懂,供
初学者参考-prepared by the use of VHDL-frequency procedures can make even the random frequency, the procedures are simple and easy to understand. reference for beginners
- 2022-02-12 09:25:12下载
- 积分:1
-
stop_watch
采用Quartus2编写的电子秒表电路
实现计时、暂停等功能(Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions)
- 2008-04-27 13:04:03下载
- 积分:1
-
VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用
VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用-CARDBUS IP CORE
- 2022-03-12 11:28:40下载
- 积分:1
-
count4
这是一个基于Quartus2 开发环境的4输入加法器( 4adder basic on Quartus2)
- 2013-08-04 09:45:07下载
- 积分:1
-
libiio-0.15
说明: ad9361 matlab驱动代码,运行此代码可在matlab中控制AD9361(AD9361 matlab driver code, running this code can control AD9361 in MATLAB)
- 2020-07-25 12:38:44下载
- 积分:1
-
hdb3
这是一个很全的HDB3译码的verilog程序,用于FPGA入门所用,verilog的入门很好的程序(This is a very wide of the HDB3 decoding verilog program for entry-FPGA used, verilog entry procedures for good)
- 2021-04-22 16:08:48下载
- 积分:1
-
circuit_timing
verilog延时电路的不同写法,和综合能否。可对比学习(Different wording verilog delay circuit, and comprehensive ability. Comparable learning)
- 2014-05-14 18:02:44下载
- 积分:1
-
ccd
自己写的一个tcd1209d的时序驱动代码,是用verilog语言编写的,可以借鉴(Of write a tcd1209d of timing-driven code, Verilog language, can learn from)
- 2021-04-08 09:39:00下载
- 积分:1