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10_ImageEdge
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)
- 2020-10-23 20:27:22下载
- 积分：1
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dds(1)
基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)
- 2017-07-11 16:36:38下载
- 积分：1
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UART1
可直接用于zedboard上的串口通信，利用zynq7000的pl部分实现一个简单的UART串口通信(Can be used directly on the zedboard serial communication, the use of zynq7000 PL part of the realization of a simple UART serial communication)
- 2020-08-14 15:18:26下载
- 积分：1
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jt2
基于FPGA的交通灯代码，VHDL语言书写。适合新手学习vhdl语言时使用(FPGA-based traffic light code, VHDL language writing. Suitable for novice learning vhdl language used when)
- 2013-10-26 13:30:26下载
- 积分：1
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mac
基于网口的收发数据及解析数据内容的verilog代码实现(Based on the Internet port to send and receive data and parse the contents of the data verilog code)
- 2017-04-24 10:13:55下载
- 积分：1
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BT1120转GTX详细设计方案
bt1120设计方案，描述了具体的方案设计以及整体的架构设计(Bt1120 design scheme, describes the specific scheme design and the overall architectural design)
- 2020-06-25 05:40:02下载
- 积分：1
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FIFO
Simulation and Synthesis Techniques for Asynchronous
FIFO Design
- 2013-08-27 16:07:08下载
- 积分：1
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uart
9针的rs232与fpga之间的串口通信源程序(Rs232 9 pin serial communication with the source between fpga)
- 2011-08-22 17:57:52下载
- 积分：1
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Quartus senior io distribution, manual example
quartus 中，高级io分配，手动的例子-Quartus senior io distribution, manual example
- 2022-07-11 02:00:46下载
- 积分：1
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21452547
加减可控制的十到十六进制计数器。完全准确，可以放心使用的(Add and subtract controllable ten to hexadecimal counter. Entirely accurate, can be at ease of use)
- 2016-01-11 12:46:04下载
- 积分：1
