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48_4.12
网络通信中的MII接口
通常将4位nibble数据送出，此程序将4位数据组合成8位数据并行输出（8比特==1个字节）。。完全可用
同时包含84转换(The MII network interface usually sent four nibble data, this procedure will be 4-bit data into 8-bit parallel output data (8 bits == 1 byte). . Completely available at the same time contains 84 conversion)
- 2009-04-21 13:43:45下载
- 积分：1
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dazhuankuai
基于FPGA设计的经典打砖块小游戏。游戏简单易玩。(FPGA design based on the classic Arkanoid game. Game easy to play.)
- 2013-11-26 09:40:37下载
- 积分：1
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VHDL-DDS
基于FPGA的DDS信号源设计，32位相位累加器，产生可调频率(FPGA-based DDS signal source design, 32-bit phase accumulator to generate tunable frequency)
- 2013-06-27 15:16:15下载
- 积分：1
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memristor
忆阻器的PSPICE仿真，是忆阻器的宏模型，适合于cadence16.5版本(memristor PSPICE simulation)
- 2021-02-20 09:39:43下载
- 积分：1
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CJQ-V1.0-fpga
实现FPGA对AD芯片AD7060的控制，程序代码的注释很多，易学易懂，适合初学者学习使用(it is good ...)
- 2013-10-10 11:20:31下载
- 积分：1
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baseband_verilog
verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器(verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter)
- 2009-10-08 10:19:34下载
- 积分：1
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led1
点亮led流水灯，通过调用锁相环，可以更改对应的时钟。(Lighting the LED pipelining lamp, the corresponding clock can be changed by calling the phase-locked loop.)
- 2020-06-16 07:00:01下载
- 积分：1
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H.265视频压缩的FPGA实现
说明： 使用verilog语言实现H.265压缩算法，能够实现实时视频数据的压缩传输(Using Verilog language to realize h.265 compression algorithm can realize the compression and transmission of real-time video data)
- 2020-06-29 02:40:01下载
- 积分：1
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median
说明： 用verilog编辑的中值滤波器！语言旁表有注释方便理解！(Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!)
- 2008-11-03 09:21:18下载
- 积分：1
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wola
WOLA polyphase filter加权跌接累加FFT信道化技术(WOLA polyphase filter bank)
- 2020-09-28 14:57:45下载
- 积分：1
