直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为...

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直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit frequency word is 20, phase word for 10, RAM used to store look-up table, its address is 10 bits wide, the data is 8 bits wide.