登录
首页 » VHDL » It s a 8051 VHDL source code issued by Original.

It s a 8051 VHDL source code issued by Original.

于 2022-06-17 发布 文件大小:220.00 kB
0 126
下载积分: 2 下载次数: 1

代码说明:

它是一个8051 VHDL源代码发布的原创。

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • VHDL出租车计价器,包含所有代码及其仿真结果
    VHDL出租车计价器,包含所有代码及其仿真结果-VHDL Taximeter that contains all the code and the simulation results
    2022-01-22 03:30:46下载
    积分:1
  • 一款verilog设计的SRAM控制器svtb_ahb_sram
    一款verilog设计的SRAM控制器,可以实现AHB总线控制的功能。(abcdefghijklmnopqrstuvwxyz)
    2020-06-30 13:40:02下载
    积分:1
  • 利用FPGA采集按键,加了消斗。其实跟单片机的效果差不多。
    利用FPGA采集按键,加了消斗。其实跟单片机的效果差不多。-The use of FPGA collect keys, plus the elimination fighting. In fact, almost with the effect of SCM.
    2023-03-12 23:10:03下载
    积分:1
  • 译码器,将八位输出转换为七段译码显示,相当于7448驱动译码管...
    译码器,将八位输出转换为七段译码显示,相当于7448驱动译码管-Decoder, the 8 output is converted to seven segment decoding shows that the equivalent of 7448
    2022-05-30 05:04:27下载
    积分:1
  • keyscan
    利用VHDL语言编写的4*4键盘扫描程序,经过测试,可以放心使用。(Using VHDL language 4* 4 keyboard scanning procedures, tested, safe to use.)
    2013-09-28 21:48:45下载
    积分:1
  • 遥控器接收解码电路
    设计遥控器接收解码电路。该电路接收编码后的串行数据,解码输出数据。电路接收 到的串行数据的格式为: 4 位同步码“ 1010”, 4 位数据(高位在前), 1 位奇校验码(对前 8 位数据校验)(Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial data received by the circuit is: 4 bit synchronous code "1010", 4 bit data (high in the front), 1 bit parity check code (check for the first 8 bits of data))
    2017-11-27 15:10:34下载
    积分:1
  • crc校验,经验证正确,下载就可直接用,有不足的地方可以指正,
    crc校验,经验证正确,下载就可直接用,有不足的地方可以指正,-CRC check, certified correct, you can download directly, there are deficiencies can correct me,
    2022-10-07 11:55:03下载
    积分:1
  • CME3000FPGADevelopment-
    针对京微雅阁的CME300 FPGA教程,里面有几个例程,并附有源代码,初学者可尽快入门。(For Beijing micro Accord CME300 FPGA tutorial, there are a few routines, with source code, beginners can start as soon as possible.)
    2013-08-19 18:01:21下载
    积分:1
  • filter
    说明:  A low pass filter module based on FPGA, easy to transplant
    2020-05-04 10:21:42下载
    积分:1
  • LMS
    least mean square algo implemented on verilog
    2017-11-01 05:01:56下载
    积分:1
  • 696518资源总数
  • 106161会员总数
  • 5今日下载