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apb timer
说明： 是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)
- 2019-01-25 16:54:02下载
- 积分：1
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Verilog 小程序源码及测试
利用Verilog编写的 小程序源码及测试,包括流水灯，交通灯 ，等小程序。
- 2022-08-03 14:04:36下载
- 积分：1
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110819_1
基于sopc的lcd时钟，开发工具为nios ii和quartus ii9.0(Based on sopc the lcd clock, development tools for the nios ii and quartus ii9.0)
- 2011-08-22 10:28:50下载
- 积分：1
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lecg_局部增强的时钟门控
这是一个关于的RTL时钟门控技术LECG此源代码是在门控时钟的应用LECG技术
- 2022-03-02 23:58:15下载
- 积分：1
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single_phase_inverter_wangyafankui
带有电网电压反馈的单相PWM整流器反馈，输出的波形很好，适合初学者学习观摩(With power grid voltage feedback single-phase PWM rectifier feedback, the output waveform is very good, suitable for beginners learning view
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- 2012-11-30 16:16:04下载
- 积分：1
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jiaotongled
该源码用vhdl语言制作了一个简单的交通灯，方便大家学习~~(The source vhdl language produced by a simple traffic light, facilitate learning ~ ~)
- 2010-11-20 14:44:36下载
- 积分：1
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VHDL-Keyboard
设计制作一个检测4*4矩阵键盘的按键编码的实验，把实际按键的键值的八位编码先转换成从0000—1111的编码，再译成数码管能识别的八位编码，在数码管动态显示时，4*4矩阵键盘的第一行对应00—03，第二行对应04—07，第三行08—11，第四行对应12—15。(Design a 4* 4 matrix keyboard key coding experiments to detect the key the actual key octet coded first convert from 0000-1111 encoding, and then translated into digital tube to identify the eight coding, digital tube dynamic display, the first line of the 4* 4 matrix keyboard corresponding to 00-03, the second line corresponds to 04-07, the third line of 08-11, the fourth line corresponds to 12-15.)
- 2012-07-01 10:02:33下载
- 积分：1
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FPGA
无线通信FPGA实现的代码 有matlab和verilog(FPGA implementation of wireless communication code matlab and verilog)
- 2012-09-17 10:39:40下载
- 积分：1
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示波器设计源工程
说明： 示波器设计，首先，AD模块对模拟信号进行采样，触发电路根据采样信号判断触发条件。满足触发条件后，连续采样一定数量的点（本系统中为640个点），存储到RAM中。峰峰值、频率计算模块对RAM中储存的波形数据进行计算，得到波形的频率以及峰峰值；VGA模块将波形显示出来，并显示计算得到的峰峰值和频率数值。(Firstly, the ad module samples the analog signal, and the trigger circuit judges the trigger condition according to the sampling signal. After meeting the trigger conditions, a certain number of points (640 points in this system) are sampled continuously and stored in RAM. The peak to peak and frequency calculation module calculates the waveform data stored in RAM to obtain the frequency and peak to peak of the waveform; the VGA module displays the waveform and displays the calculated peak to peak and frequency values.)
- 2021-01-02 17:29:54下载
- 积分：1
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Verilog-learning-experience
初学学习verilog的经验，可以帮助新手以正确的思维方式，学习方法学习。(Verilog learning experience)
- 2013-09-30 09:51:04下载
- 积分：1
