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alu3
用verilog语言编写,一个8-bit ALU,可以完成按字节的+、-和与、或、非操作(Using Verilog language, an 8-bit ALU, to be completed by byte+,- And, or, non-operating)
- 2008-05-12 12:48:49下载
- 积分:1
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al422b
AL422B,FPGA写的控制时序。XIWANGDUIDAJIAYOUYONG(AL422B,timing of AL422b.)
- 2014-04-17 21:41:09下载
- 积分:1
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COMPLETE-OFDM
完整的OFDM仿真程序,包括QPSK,16QAM调制,基于MATLAB,各个步骤都有详细的说明。(OFDM simulation program, based on the complete MATLAB, every step is described in detail.)
- 2013-05-23 11:31:57下载
- 积分:1
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my
说明: 64位数据的CRC-32校验的,Verilog实现,算法并行优化(64-bit data CRC-32 checksum, Verilog implementation of a parallel optimization algorithm)
- 2011-09-17 19:36:16下载
- 积分:1
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16b20b_Encoder
16b20b encoder and decoder
- 2013-02-04 13:24:46下载
- 积分:1
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9826
针对AD9826驱动设计的Verilog代码,主要是配置ccd采样的设计(The Verilog code is designed for AD9826, to configuration ccd sampling )
- 2020-07-16 21:48:50下载
- 积分:1
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DA_TLC5620
是基于FPGA的5620的数模转换芯片底层的应用程序,希望有用。(Is a digital-analog converter chip underlying the 5620 FPGA-based applications, and I hope useful.)
- 2013-12-15 10:43:21下载
- 积分:1
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AES_128
AES 128 bit with various device interface on FPGA
- 2021-03-09 17:59:27下载
- 积分:1
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FPGASquare-RootRaised-CosineFilter
数字通信系统中, 基带信号的频谱一般较宽, 因此
传递前需对信号进行成形处理, 以改善其频谱特性,使
得在消除码间干扰与达到最佳检测接收的前提下,提高信道的频带利用率。目前,数字系统中常使用的波形成形滤波器有平方根升余弦滤波器、 高斯滤波器等。设计方法有卷积法或查表法, 其中: 卷积法的实现,需要消耗大量的乘法器与加法器,以构成具有一定延时的流水线结构。为降低硬件消耗,文献提出了一种分(FPGA Implementation of Square Root Raised Cosine Pulse Shaping Filter)
- 2011-05-04 21:23:36下载
- 积分:1
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vgac_sst160aN
基于fpga和sopc的用VHDL语言编写的EDA的32位Nios CPU嵌入式系统及其DMA设计俄罗斯方块游戏机(FPGA and SOPC based on the use of VHDL language EDA 32-bit Nios CPU and the DMA design of embedded systems Tetris game)
- 2021-04-11 11:18:58下载
- 积分:1