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Dec_mul
时间同步后即可确定每帧数据的起始位置，这样就能完整的截取下每一帧。但是，数据中还带有频偏信息。在常规的通信系统中，多普勒很小仅仅会带来很小的频偏，但是在大多普勒的情况下，频偏将非常大，20马赫的速度将会带来将近34K的频偏。因此，如何很好的纠正频偏即为本系统的难点。
OFDM中，我们将大于子载波间隔倍数的频偏称为整数倍频偏，而将小于一个子载波间隔的频偏称为小数倍频偏。频偏矫正精度只要能保证小于十分之一倍的子载波间隔，频偏就不会对均衡和解调造成影响。本文中我们借鉴这种思想，由于硬件资源限制，我们将在接收端做64点FFT，即相当于将频域划分为64份，我们将小于 的频偏称为小数倍频偏，将 整数倍的频偏称为整数倍频偏。本程序即基于SCHIMDL经典方法完成小数倍频偏纠正(After time synchronization can determine the starting position of each frame data, so you can complete the interception of each frame. However, in the data with frequency information. In conventional communication systems, doppler small will bring only small deviation, but in the case of most of the doppler, frequency PianJiang is very large, 20 Mach speed will lead to deviation of nearly 34 k. Therefore, how to good to correct deviation is the difficulty of this system.
OFDM, we will be bigger than the sub-carrier spacing ratio of frequency deviation is called the integer frequency offset, and the interval will be less than a child carrier frequency offset is called decimal frequency doubling. Deviation is less than one over ten times as long as can guarantee accuracy of sub-carrier spacing, deviation will not affect balance and demodulation. This article, we draw lessons from the idea, due to the limited hardware resources, we will do 64 points FFT at the receiving end, which is equ)
- 2013-12-26 18:00:24下载
- 积分：1
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rmii
rmii 以太网接口时序源代码，值得开发借鉴的哦(verilog hdl)
- 2013-10-12 09:56:24下载
- 积分：1
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dr6—ise-F
用FPGA开发板的按键作为电子表的时间初值设置控制信号，数码管当前时间值输出。用按键选择分别输出：分、秒、1/10秒。(With FPGA development board button, as the time value of the electronic table, set the control signal, digital tube current time value output. Select output by buttons: minutes, seconds, and 1/10 seconds.)
- 2017-10-11 21:19:55下载
- 积分：1
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hdb3
这是一个很全的HDB3译码的verilog程序，用于FPGA入门所用，verilog的入门很好的程序(This is a very wide of the HDB3 decoding verilog program for entry-FPGA used, verilog entry procedures for good)
- 2021-04-22 16:08:48下载
- 积分：1
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cam2
DE2-115 + D5M Camera to VGA PC
- 2020-07-09 19:48:55下载
- 积分：1
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FPGA_Based_CNN-master
这个项目是一个基于FPGA的alexnet第一卷积层实现。(This project is a FPGA based implementation of first Convolutional Layer of AlexNet.)
- 2017-08-27 11:00:48下载
- 积分：1
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CPU
十一和通过vivado实现多周期cpu，各种作业再里面包含了(Realizing multi period CPU)
- 2020-12-29 10:19:00下载
- 积分：1
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PIC单片机学习软件及其资料
说明： PIC单片机学习软件及其资料，入门到精通(PIC MCU learning software and its information, entry to proficiency)
- 2019-07-04 17:17:40下载
- 积分：1
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智能交通控制系统
在交通灯系统中（图1）,路口A、B、C、D均需要红、黄、绿、左转四盏灯(用RYGL分别表示) ,并且每个路口都需要一个倒数的计时器,假设绿灯每次维持的时间是45 s ,在亮绿灯的最后5s亮黄灯5s作为提示 ,左转灯15s，在亮左转灯的最后5s亮黄灯5 s作为提示 ，红灯60s。交通灯系统大多是自动控来指挥交通的,但有时需要由交警手动控制红绿灯,所以要求设计的该交通信号系统需要具有该功能。
- 2022-07-04 05:00:48下载
- 积分：1
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Interleaver_Deinterleaver
通信中卷积交织/解交织FPGA源程序，采用verilogHDL代码实现，包含测试程序，经过验证。(Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.)
- 2021-04-17 15:18:53下载
- 积分：1
