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Motion_control
基于FPGA的运动控制系统设计，包含位置、速度控制等(motion control)
- 2020-11-29 13:09:28下载
- 积分：1
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CPU_Project_board
CPU 5级流水线实现（加hazard处理与板级验证，板级验证带有按键消抖）(5-stage pipelined CPU (plus hazard dealing with board-level verification, board-level verification with key debounce))
- 2020-12-03 09:29:25下载
- 积分：1
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code
Due to its high modularity and carry-free addition, a redundant
binary (RB) representation can be used when designing high performance
multipliers. The conventional RB multiplier requires an additional RB partial
product (RBPP) row, because an error-correcting word (ECW) is generated
by both the radix-4 Modified Booth encoding (MBE) and the RB encoding.
This incurs in an additional RBPP accumulation stage for the MBE multiplier.
In this paper, a new RB modified partial product generator (RBMPPG) is
proposed; it removes the extra ECW and hence, it saves one RBPP
accumulation stage.
- 2017-10-01 23:34:56下载
- 积分：1
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AND
this is "AND" gate implementation in VHDL
- 2012-12-23 00:59:12下载
- 积分：1
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EDK_Tutorial_1
EDK tutorial 1 ----------------
- 2013-04-04 10:18:46下载
- 积分：1
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uartverilog
实现FPGA多字节的稳定串口通信，改编自特权同学的FPGA代码(Realize the stable serial communication of multi-byte FPGA and adapt the FPGA code from Quan via Quartus by Verilog)
- 2020-11-16 08:39:40下载
- 积分：1
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29_ad9226_test
用Verilog编写ad_9866的相应程序，在FPGA上实现相应功能(The corresponding program of ad_9866 is written with Verilog, and the corresponding functions are realized on the FPGA.)
- 2019-06-24 16:43:27下载
- 积分：1
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multiplexerr verilog test bench
my code be helpful for someone, and in fact, do not download it
- 2018-07-04 02:08:12下载
- 积分：1
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5956474temperature
DS18b20 temperature sensor vhdl code
- 2010-07-04 03:46:44下载
- 积分：1
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huffman
huffman transform in vhdl language
- 2013-08-26 13:17:15下载
- 积分：1
