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multiply
由verilog编写的乘法器，通过两个文件的调用实现。由于子模块的调用使得程序简化了许多。(Prepared by the Verilog multiplier, through the realization of the two documents call. As the sub-modules to simplify the procedure call makes a lot.)
- 2008-12-30 20:51:33下载
- 积分：1
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shuzishizhong
基于DE2-115开发板设计的一个数字钟，能进行正常的小时、分、秒计时功能，并分别由开发板上面的数码管显示秒（60s）、分（60min）、小时（24hours）的时间。并具有手动调整时间的功能(DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board digital display seconds (60s), points (60min), hours (24hours) time . And has a function to manually adjust the time)
- 2020-11-01 11:39:54下载
- 积分：1
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Carry look ahead adder with saturating arithmetic
用Verilog实现的16位进位先行加法器。实现了饱和算法。
- 2023-01-16 01:15:03下载
- 积分：1
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LDPC编译码
LDPC编译码，最新一代纠错码技术，自带校验矩阵，数据程序内带测试数据
- 2022-01-26 04:09:36下载
- 积分：1
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I2S_2
that file is different I2S example
- 2014-11-27 06:39:52下载
- 积分：1
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1位ADPCM编解码器：：概述
音频编码（ADPCM位） ；
- 2022-01-26 03:09:33下载
- 积分：1
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fm_parcial
this is a simulation fm in simulink mathlab this is one program with pll
- 2012-11-30 10:02:10下载
- 积分：1
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DTMB
能够完美产生数字地面电视（DTMB）的信源的程序。帧头模式为模式一。信道可选择，信号加入频偏，延时，后经滤波器后输出。(Able to produce perfect digital terrestrial television (DTMB) of the source program. Mode is the mode a header. Channels to choose from, the signal adding offset, delay, after the filter output.)
- 2013-07-25 11:22:28下载
- 积分：1
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Verilog-learning-experience
初学学习verilog的经验，可以帮助新手以正确的思维方式，学习方法学习。(Verilog learning experience)
- 2013-09-30 09:51:04下载
- 积分：1
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application-in-card-and-servo-drive
AB相编码器解码接口_PWM输出SOPC方案及其在运动控制卡和伺服驱动器中的应用(AB phase encoder decoder interface _PWM output SOPC program and its application in motion control card and servo drive)
- 2012-03-22 12:44:52下载
- 积分：1
